Turn-off power semiconductor device with gate runners

A turn-off power semiconductor device comprising:

• a semiconductor wafer having a first main side and a second main side opposite to the first main side;
• a plurality of thyristor cells;
• a common gate contact arranged on the first main side;
• and
• a plurality of stripe-shaped electrically conductive first gate runners, each first gate runner having a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion, wherein the first end portion is directly connected to the common gate contact and a longitudinal main axis of each first gate runner extends in a lateral direction away from the common gate contact;
• wherein each thyristor cell comprises in an order from the first main side to the second main side:
• a first emitter layer portion of a first conductivity type;
• a first base layer portion of a second conductivity type different from the first conductivity type, the first emitter layer portion being in direct contact with the first base layer portion to form a first p-n junction between the first base layer portion and the first emitter layer portion;
• a second base layer portion of the first conductivity type, wherein the first base layer portion is in direct contact with the second base layer portion to form a second p-n junction between the first base layer portion and the second base layer portion;
• and
• a second emitter layer portion of the second conductivity type separated from the first base layer portion by the second base layer portion, wherein the second base layer portion is in direct contact with the second emitter layer portion to form a third p-n junction between the second base layer portion and the second emitter layer portion,
• a first gate electrode layer portion arranged lateral to the first emitter layer portion, the first gate electrode layer portion forming an ohmic contact with the first base layer portion;
• a first main electrode layer portion arranged on the first main side and forming an ohmic contact with the first emitter layer portion;
• and
• a second main electrode layer portion arranged on the second main side and forming an ohmic contact with the second emitter layer portion;
• wherein the plurality of thyristor cells comprises a plurality of first thyristor cells and a plurality of second thyristor cells;
• wherein the first emitter layer portion of each first thyristor cell has a distance from the common gate contact that is smaller than a predetermined distance and the first emitter layer portion of each second thyristor cell has a distance from the common gate contact that is larger than the predetermined distance;
• wherein the first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer laterally surrounding the first main electrode layer portions of all first thyristor cells;
• wherein the first gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer;
• wherein the first gate electrode layer is directly connected to the common gate contact such that the first gate electrode layer portion of each first thyristor cell is electrically connected to the common gate contact;
• wherein the second end portion of each first gate runner is directly connected to the second gate electrode layer;
• wherein a length of each first gate runner in a radial direction is at least two times a maximal length of the first emitter layer portions of any first thyristor cell;
• wherein a thickness of each first gate runner in a direction perpendicular to the lateral direction is at least 25% greater than a thickness of the first gate electrode layer at a position in a middle between two adjacent first emitter layer portions, wherein a thickness direction is a direction perpendicular to the second main side;
• wherein the common gate contact is ring-shaped in an orthogonal projection onto a plane parallel to the second main side and the longitudinal main axis of each first gate runner extends in a radial direction from the common gate contact towards a lateral center of the semiconductor wafer;
• wherein, in the orthogonal projection onto the plane parallel to the second main side, a first ring-shaped gate electrode layer portion of the second gate electrode layer is arranged inside the ring-shaped common gate contact to laterally surround a remaining portion of the second gate electrode layer, wherein each first gate runner connects the common gate contact with the first ring-shaped electrode layer portion;
• wherein at least the first connecting portion of each first gate runner is separated from the first gate electrode layer, so that any electrically conducting path from the first connecting portion of the each first gate runner to the first gate electrode layer passes at least through one of the first end portion of a same first gate runner, the second end portion of the same first gate runner and the semiconductor wafer;
• and
• wherein an outer circumferential edge of the first ring-shaped gate electrode layer portion is separated from the first gate electrode layer so that any electrically conducting path from the second gate electrode layer passes at least through the semiconductor wafer or through one of the plurality of first gate runners.

A turn-off power semiconductor device comprising:

• a semiconductor wafer having a first main side and a second main side opposite to the first main side;
• a plurality of thyristor cells;
• a common gate contact arranged on the first main side;
• and
• a plurality of stripe-shaped electrically conductive first gate runners, each first gate runner having a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion, wherein the first end portion is directly connected to the common gate contact and a longitudinal main axis of each first gate runner extends in a lateral direction away from the common gate contact;
• wherein each thyristor cell comprises in an order from the first main side to the second main side:
• a first emitter layer portion of a first conductivity type;
• a first base layer portion of a second conductivity type different from the first conductivity type, the first emitter layer portion being in direct contact with the first base layer portion to form a first p-n junction between the first base layer portion and the first emitter layer portion;
• a second base layer portion of the first conductivity type, wherein the first base layer portion is in direct contact with the second base layer portion to form a second p-n junction between the first base layer portion and the second base layer portion;
• and
• a second emitter layer portion of the second conductivity type separated from the first base layer portion by the second base layer portion, wherein the second base layer portion is in direct contact with the second emitter layer portion to form a third p-n junction between the second base layer portion and the second emitter layer portion,
• a first gate electrode layer portion arranged lateral to the first emitter layer portion, the first gate electrode layer portion forming an ohmic contact with the first base layer portion;
• a first main electrode layer portion arranged on the first main side and forming an ohmic contact with the first emitter layer portion;
• and
• a second main electrode layer portion arranged on the second main side and forming an ohmic contact with the second emitter layer portion;
• wherein the plurality of thyristor cells comprises a plurality of first thyristor cells and a plurality of second thyristor cells;
• wherein the first emitter layer portion of each first thyristor cell has a distance from the common gate contact that is smaller than a predetermined distance and the first emitter layer portion of each second thyristor cell has a distance from the common gate contact that is larger than the predetermined distance;
• wherein the first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer laterally surrounding the first main electrode layer portions of all first thyristor cells;
• wherein the first gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer;
• wherein the first gate electrode layer is directly connected to the common gate contact such that the first gate electrode layer portion of each first thyristor cell is electrically connected to the common gate contact;
• wherein the second end portion of each first gate runner is directly connected to the second gate electrode layer;
• wherein the common gate contact is ring-shaped in an orthogonal projection onto a plane parallel to the second main side and the longitudinal main axis of each first gate runner extends in a radial direction from the common gate contact towards a lateral center of the semiconductor wafer;
• wherein, in the orthogonal projection onto the plane parallel to the second main side, a first ring-shaped gate electrode layer portion of the second gate electrode layer is arranged inside the ring-shaped common gate contact to laterally surround a remaining portion of the second gate electrode layer, wherein each first gate runner connects the common gate contact with the first ring-shaped electrode layer portion;
• wherein at least the first connecting portion of each first gate runner is separated from the first gate electrode layer, so that any electrically conducting path from the first connecting portion of the each first gate runner to the first gate electrode layer passes at least through one of the first end portion of a same first gate runner, the second end portion of the same first gate runner and the semiconductor wafer;
• wherein an outer circumferential edge of the first ring-shaped gate electrode layer portion is separated from the first gate electrode layer so that any electrically conducting path from the second gate electrode layer passes at least through the semiconductor wafer or through one of the plurality of first gate runners;
• wherein the plurality of thyristor cells further comprises a plurality of third thyristor cells, wherein the first emitter layer portion of each third thyristor cell has a distance from the common gate contact that is greater than a distance of each one of the first emitter layer portions of the first thyristor cells and of the second thyristor cells from the common gate contact;
• wherein third gate electrode layer portions of all third thyristor cells are implemented as a third gate electrode layer;
• wherein a second ring-shaped gate electrode layer portion of the third gate electrode layer is arranged inside of the ring-shaped common gate contact to laterally surround a remaining portion of the third gate electrode layer;
• wherein the first gate electrode layer and the second gate electrode layer are arranged outside of the second ring-shaped gate electrode layer portion;
• wherein the turn-off power semiconductor device further comprises a plurality of stripe-shaped electrically conductive second gate runners, each second gate runner having a third end portion, a fourth end portion opposite to the third end portion and a second connecting portion connecting the third end portion and the fourth end portion;
• wherein the third end portion of each second gate runner is connected to the first ring-shaped electrode layer portion and the fourth end portion of each second gate runner is connected to the second ring-shaped electrode layer portion;
• and
• wherein at least the second connecting portion of each second gate runner is separated from the second gate electrode layer so that any electrically conducting path from the second connecting portion of each second gate runner to the second gate electrode layer passes at least through one of the third end portion of a same second gate runner, the fourth end portion of the same second gate runner and the semiconductor wafer.