Layer-to-layer registration measurement mark

A multilayer printed circuit board comprising:

• a first conducting layer (CL) and a second CL, the first CL being separated from the second CL by a first non-conducting layer (NCL);
• at least three first measurement mark areas (MMAs) in the first CL and at least three second MMAs in the second CL, the at least three first MMAs individually overlapping with the at least three second MMAs;
• and
• a first polygonal measurement mark (MM) in each of the at least three first MMAs;
• and
• a second polygonal MM and a third polygonal MM in each of the at least three second MMAs,
• wherein the second polygonal MM is positioned along an extended first angle bisector bisecting a first vertex of the first polygonal MM and a first vertex of the second polygonal MM close to the first polygonal MM is substantially aligned with the first vertex of the first polygonal MM, and
• wherein the third polygonal MM is positioned along an extended second angle bisector bisecting a second vertex of the first polygonal MM and a first vertex of the third polygonal MM close to the first polygonal MM is substantially aligned with the second vertex of the first polygonal MM.

A method of measuring layer-to-layer registration comprising:

• providing a multilayer printed circuit board having a first polygonal measurement mark (MM) in a first measurement mark area (MMA) of a first conducting layer (CL) and a second polygonal MM in a second MMA of a second CL, the first polygonal MM having a vertex with a first side A1 and a second side B1 and the second polygonal MM having a vertex with a first side A2 and a second side B2, the first side A1 being parallel to the first side A2 and the second side B1 being parallel to the second side B2,
• measuring a first distance dX between the first side A1 and the first side A2;
• measuring a second distance dY between the second side B1 and the second side B2;
• and
• calculating a mark misalignment dR from the first distance dX and the second distance dY.