Accelerated polynomial coding system and method

A system adapted to use accelerated error-correcting code (ECC) processing to improve the storage and retrieval of digital data distributed across a plurality of drives, comprising:

• at least one processor comprising at least one single-instruction-multiple-data (SIMD) processing core that executes SIMD instructions loaded from at least one non-volatile storage medium and loads original data from a memory and stores check data to the memory, the SIMD processing core comprising a plurality of vector registers, each of the vector registers storing at least 16 bytes;
• a plurality of data drives each comprising at least one non-volatile storage medium that stores at least one block of the original data, the at least one block comprising at least 512 bytes;
• more than two check drives each comprising at least one non-volatile storage medium that stores at least one block of the check data;
• and
• at least one input/output (I/O) controller that stores the at least one block of the check data from the memory to the check drives,
• wherein the processor, the SIMD instructions, the at least one non-volatile storage medium, and the I/O controller implement a polynomial coding system comprising a linear feedback shift register (LFSR) sequencer that:
• initializes a plurality of values of the LFSR, the plurality of values being ordered from a least significant value to a most significant value, the plurality of values being stored in one or more of the vector registers;
• for each data symbol of a sequence of data symbols of the original data:
• adds the data symbol to the most significant value to compute a new input to the LFSR;
• shifts the new input into the LFSR;
• and
• updates the plurality of values of the LFSR based on previous values of the LFSR;
• and
• outputs the plurality of values of the LFSR as a plurality of check symbols of the check data.

A system adapted to use accelerated error-correcting code (ECC) processing to improve the storage and retrieval of digital data distributed across a plurality of drives, comprising:

• at least one processor comprising at least one single-instruction-multiple-data (SIMD) processing core that executes SIMD instructions loaded from at least one non-volatile storage medium and loads received original data and received check data from a memory and computes syndrome data, the SIMD processing core comprising at least 16 vector registers, each of the vector registers storing at least 16 bytes;
• a plurality of data drives each comprising at least one non-volatile storage medium that stores at least one block of the received original data, the at least one block comprising at least 512 bytes;
• more than two check drives each comprising at least one non-volatile storage medium that stores at least one block of the received check data;
• and
• at least one input/output (I/O) controller that reads at least one block of the received check data from the check drives and stores the at least one block of the received check data to the memory,
• wherein the processor, the SIMD instructions, the at least one non-volatile storage medium, and the I/O controller implement a polynomial coding system, comprising a parallel syndrome sequencer that:
• initializes a first check vector with a first symbol of a sequence of symbols of a codeword comprising symbols of the received original data and symbols of the received check data;
• initializes a second check vector with a Galois field (GF) product of the first symbol and a constant multiplicand stored in a vector register;
• for each symbol other than the first symbol of the sequence of symbols of the codeword:
• GF adds the symbol to the first check vector and the second check vector;
• and
• GF multiplies the second check vector by the constant multiplicand;
• computes error values based on the first check vector based on values that are non-zero;
• and
• computes error locations by computing a log of a quotient of the first check vector and the second check vector.