Dual-trip point data slicer for serial data demodulation

A circuit configured to operate as a data slicer, the circuit comprising:

• an input port configured to receive an input signal;
• a first output port electrically coupled to the input port by a first circuit path;
• a second output port electrically coupled to the input port by a second circuit path that is parallel to the first circuit path;
• the first circuit path configured to provide the input signal from the input port to the first output port;
• the second circuit path configured to provide a reference signal to the second output port, the reference signal being based on a delayed version of the input signal;
• and
• a comparator electrically coupled to the first output port and the second output port, the comparator configured to receive the input signal as a first input via the first output port, to receive the reference signal as a second input via the second output port, and to generate a digital output based on whether a voltage of the input signal exceeds a voltage of the reference signal.