Delay-locked loop, delay locking method, clock synchronization circuit, and memory

A delay locking method, comprising:

• receiving an initial clock signal externally and outputting an input clock signal on the basis of the initial clock signal, wherein a clock cycle of the initial clock signal is the same as the clock cycle of the input clock signal;
• receiving the input clock signal and performing frequency division on the input clock signal to obtain an intermediate clock signal, wherein a clock cycle of the intermediate clock signal is twice a clock cycle of the input clock signal;
• adjusting and transmitting the intermediate clock signal through a first adjustable delay line to obtain a synchronous clock signal, and performing delay transmission on the input clock signal to obtain a sampling clock signal;
• and
• latching the synchronous clock signal on the basis of the sampling clock signal to obtain a group of target clock signals, wherein a phase difference between two adjacent target clock signals in the group of target clock signals is a preset value.

A clock synchronization circuit, comprising a delay-locked loop and a data selection module, wherein a signal transmission path is arranged between the delay-locked loop and the data selection module;

• wherein the delay-locked loop comprises:
• a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal, wherein a clock cycle of the intermediate clock signal is twice a clock cycle of the input clock signal;
• a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal;
• a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal;
• and
• a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals;
• wherein, a phase difference between two adjacent target clock signals in the group of target clock signals is a preset value;
• wherein the data selection module is configured to:
• receive the group of target clock signals through the signal transmission path, and perform sampling and selective outputting on a data signal by using the group of target clock signals, so as to output a target data signal.