Method for programming an FPGA

A method for programming an FPGA, wherein a library, which includes elementary operations, executable on the FPGA, and a particular latency table for each of the elementary operations of the library is provided, each latency table indicating the latency of the particular operation for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the particular operation during the execution on the FPGA, depending on the input bit width of the particular operation and the clock rate of the FPGA, the method comprising:

• defining a data path, the data path indicating a consecutive execution of at least two elementary operations of the library on the FPGA;
• detecting the latencies given for the particular input bit width of the particular elementary operations of the data path for a plurality of different clock rates in the latency tables, and adding up the detected latencies for each clock rate, so that a total latency for the data path results in each case for this plurality of different clock rates;
• and
• selecting one of the clock rates from the plurality of different clock rates for operating the FPGA, depending on the particular total latency of the particular clock rates.