Bandwidth enhanced gain stage with improved common mode rejection ratio

An amplifier, comprising a gain stage, wherein the gain stage comprises:

• a differential input transconductor comprising a first transistor and a second transistor, wherein the first and second transistors have respective control nodes configured to receive an input signal;
• a loading network directly connected to output nodes of the first and second transistors, the loading network comprising a first pair of inductors directly connected in series with a pair of load resistors, wherein the first pair of inductors are mutually coupled;
• a differential output terminal coupled to the loading network;
• and
• a second pair of inductors connected between the differential input transconductor and the differential output terminal, wherein inductors of the second pair of inductors are mutually coupled.

An amplifier comprising:

• a first input transistor;
• a second input transistor;
• a load network comprising a first terminal coupled to an output node of the first input transistor, a second terminal coupled to an output node of the second input transistor, and a power supply terminal configured to be coupled to a power supply node, the load network comprising:
• a first resistor coupled in series with a first inductor between the first terminal and the power supply terminal, and
• a second resistor coupled in series with a second inductor between the second terminal and the power supply terminal, wherein the second inductor is mutually coupled to the first inductor;
• a third inductor conductively coupled between the first terminal of the load network and a first output node;
• and
• a fourth inductor conductively coupled between the second terminal of the load network and a second output node, wherein the fourth inductor is mutually coupled to the third inductor.