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US 12,340,858 B2Granted
Apparatuses, systems, and methods for module level error correction
AssigneeMicron Technology, Inc.
InventorSujeet Ayyapureddi
Life of this patent
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Abstract
Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.
Claims16
An apparatus comprising:
- a first memory device including a mode register;
- module logie including a module settings register;
- a plurality of data bus lines coupling the first memory device to the module logic, wherein a signaling protocol used to carry data between the module logic and the first memory device along the plurality of data bus lines is selected from a plurality of signaling protocols based on the mode register and the module settings register and wherein the module settings register includes a multi-level signaling setting which enables multi-level signaling along at least some of the plurality of data bus lines and wherein the multi-level signaling includes providing the data along the at least some of the plurality of data bus lines as a signal where more than two voltage levels are used to represent more than two logical states of the signal, and
- a plurality of parity bus lines coupling the first memory device to the module logic, wherein the plurality of parity bus lines are configured to provide parity bits of a codeword to or from the first memory device and the plurality of data bus lines are configured to provide data bits of the codeword to or from the first memory device.
1 more element
An apparatus comprising:
- a plurality of memory devices each configured to provide a respective one of a plurality of codewords as part of an access operation;
- module logic including:
- a module error correction code (ECC) circuit configured to detect errors in the plurality of codewords when enabled;
- and
- a module settings register configured to store a module ECC enable value, wherein the ECC circuit is enabled based on the module ECC enable value;
- a plurality of parity buses, wherein at least two parity buses of the plurality of parity buses are configured to couple a respective one of the plurality of memory devices to the module logic, and wherein the plurality of parity buses are configured to provide parity bits of the plurality of codewords to or from respective ones of the plurality of memory devices;
- and
- a plurality of data buses each configured to couple a respective one of the plurality of memory devices to the module logic, wherein each of the plurality of codewords includes data bits and wherein the plurality of data buses are configured to carry the data bits,
- wherein the module settings register includes at least one signaling protocol value, and wherein a signaling protocol along the plurality of data buses is selected from a plurality of signaling protocols based on the at least one signaling protocol value, and wherein the signaling protocol value includes a multi-level signaling setting which enables multi-level signaling along at least some of the plurality of data bus lines and wherein the multi-level signaling includes providing the data along the at least some of the plurality of data bus lines as a signal where more than two voltage levels are used to represent more than two logical states of the signal.
6 more elements
A method comprising:
- selecting a signaling protocol from a plurality of signaling protocols to carry data between a module logic of a module and a memory device of a plurality of memory devices based on a setting in a module settings register and a mode register of the memory device, wherein the selected signaling protocol is a multi-level signaling protocol corresponding to a multi-level signal setting in the module settings register:
- enabling, according to the multi-level signaling protocol, multi-level signaling along at least some of a plurality of data bus lines coupling the memory device to the module logic. wherein the multi-level signaling includes providing the data along the at least some of the plurality of data bus lines as a signal where more than two voltage levels are used to represent more than two logical states of the signal;
- receiving a plurality of codewords each from a respective one of the plurality of memory devices using the multi-level signaling protocol, wherein each of the plurality of codewords includes data bits and parity bits, and wherein the data bits are received along a plurality of data buses and the parity bits are received along a plurality of parity buses;
- enabling a module error correction code (ECC) circuit based on a setting in the module settings register;
- and
- detecting errors in the plurality of codewords with the ECC circuit when the ECC is enabled.
3 more elements
Dependencies are inferred from the claim text.