Drive circuit with improved timing margin for memory device

A memory device comprising:

• a memory cell coupled to a first bit line and a second bit line;
• a drive circuit including a first transistor coupled between the first bit line and a first metal rail providing a first reference voltage;
• a pre-charge circuit including a second transistor coupled between the first bit line and a second metal rail providing a second reference voltage;
• a NOR gate including i) a first input to receive a first control signal, and ii) a second input to receive an input signal, an output of the NOR gate coupled to a gate electrode of the first transistor;
• an OR gate including i) a first input to receive the first control signal, and ii) a second input to receive the input signal;
• and
• a NAND gate including i) a first input to receive a second control signal, and ii) a second input coupled to an output of the OR gate, an output of the NAND gate coupled to a gate electrode of the second transistor.

A method comprising:

• pre-charging, by a memory device, a first bit line and a second bit line coupled to a memory cell, in response to a first control signal having a first state and a second control signal having a second state, the first control signal indicating whether to apply a data signal to the memory cell to write data at the memory cell, the second control signal indicating whether to pre-charge the first bit line and the second bit line;
• determining, by the memory device, to provide a transitioning phase, according to the first control signal having a third state and the second control signal having the second state;
• disabling, by the memory device, i) an equalizer to electrically decouple the first bit line from the second bit line, and ii) a pre-charge circuit to bypass setting a first voltage at the first bit line and a second voltage at the second bit line to a predetermined voltage level, in the transitioning phase;
• and
• enabling, by the memory device, a drive circuit to apply the data signal to the memory cell to write the data at the memory cell, while the equalizer and the pre-charge circuit are disabled, in response to the first control signal having the third state and the second control signal having a fourth state.