US 12,340,832 B2Granted

Circuitry borrowing for memory arrays

AssigneeMicron Technology, Inc.

InventorsAndrea Martinelli, Francesco Mastroianni, Kiyoshi Nakai

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Abstract

Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

Claims20

Dependent claims

An apparatus, comprising:

a memory array comprising a plurality of memory sections, wherein the plurality of memory sections comprises a first edge section at a first edge of the memory array, a second edge section at a second edge of the memory array, and a plurality of interior sections between the first edge section and the second edge section;
a plurality of sets of shared circuitry that are each common to a respective first memory section of the plurality of memory sections and a respective second memory section of the plurality of memory sections;
a first driver of a first type corresponding to the first edge section, wherein the first driver is coupled with a first set of the plurality of sets of shared circuitry that is common to the first edge section and a first interior section of the plurality of memory sections;
a second driver of a second type corresponding to the second edge section, wherein the second driver is coupled with a second set of the plurality of sets of shared circuitry that is common to the second edge section and a second interior section of the plurality of memory sections, and wherein the first edge section occupies a first area that does not overlap with any driver of the second type and the second edge section occupies a second area that does not overlap with any driver of the first type;
and
a first set of drivers underlying the first interior section and coupled with a third set of circuitry of the plurality of sets of shared circuitry, wherein the first set of drivers comprises one or more drivers of the first type and one or more drivers of the second type, and wherein the third set of circuitry is configured to be selectively coupled with the first interior section and a third interior section of the plurality of memory sections.

3 more elements

An apparatus, comprising:

a memory array comprising a plurality of memory sections, where the plurality of memory sections comprises a first edge section, a first interior section, a second interior section, and a second edge section;
a first set of circuitry configured to be selectively coupled with the first edge section and the first interior section;
a second set of circuitry configured to be selectively coupled with the second interior section and the second edge section;
a first driver of a first type underlying the first edge section, wherein the first driver is coupled with the first set of circuitry;
a second driver of a second type underlying the second edge section, wherein the second driver is coupled with the second set of circuitry, and wherein no driver of the second type underlies the first edge section and no driver of the first type underlies the second edge section;
a third set of circuitry configured to be selectively coupled with the first interior section and a third interior section of the plurality of memory sections;
and
a first set of drivers underlying the first interior section and coupled with the third set of circuitry, wherein the first set of drivers comprises one or more drivers of the first type and one or more drivers of the second type.

5 more elements

A method, comprising:

identifying a first memory section of a memory array for an access operation, the first memory section located between a second memory section of the memory array and a first edge section of the memory array;
operating, based at least in part on the identifying, a first set of circuitry shared by the first memory section and the first edge section using drivers of a first type associated with the first edge section and drivers of a second type associated with the first memory section, wherein the first edge section occupies an area that does not overlap with any driver of the second type;
operating, based at least in part on the identifying, a second set of circuitry shared by the first memory section and the second memory section using drivers of the first type associated with the first memory section and drivers of the second type associated with the second memory section;
and
performing the access operation based at least in part on operating the first set of circuitry and operating the second set of circuitry.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/563,389Filed 28 Dec 2021 · continuation
Priority: 11 Jul 2019
Published: US 2022/0199137 A123 Jun 2022
Granted: 24 Jun 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

G11C 11/2255
Address circuits or decoders: bit-line or column circuits
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 7/08
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: control thereof
G11C 7/1063
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: control signal…

Family

Application16/508,772Parent of this continuation · filed 11 Jul 2019
US 2022/0199137 A1Pre-grant publication · published 23 Jun 2022
US 11,217,291 B2Parent of this continuation
US 2021/0012825 A1Published application
US 12,340,832 B2This patent

From the US filing history. Foreign family members aren’t listed.