Partial sum management and reconfigurable systolic flow architectures for in-memory computation

A method of neural network processing, comprising:

• receiving, at a first input of a multiplexer, first data from a write register;
• receiving, at a second input of the multiplexer, second data from a flip-flop array;
• receiving, at an accumulator circuit, third data from a processing element (PE) circuit;
• selecting, with the multiplexer, data to output to the accumulator circuit between the first data and the second data;
• and
• accumulating, with the accumulator circuit, the selected output data from the multiplexer and the third data received from the PE circuit to generate accumulated data,
• wherein the PE circuit comprises:
• an adder circuit;
• and
• an accumulator-and-shifter circuit having an input coupled to an output of the adder circuit and having an output coupled to an input of the accumulator circuit.