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US 12,340,219 B2Granted
FPGA specialist processing block for machine learning
AssigneeAltera Corporation
InventorsMartin Langhammer, Dongdong Chen, Jason R. Bergendahl
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Abstract
The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
Claims20
A digital signal processing (DSP) block comprising:
- a plurality of inputs configurable to receive a first plurality of weight values and a second plurality of weight values wherein:
- in a first mode of operation, the first plurality of weight values and the second plurality of weight values are received via a first portion of the plurality of inputs coupled to a first portion of programmable logic;
- and
- in a second mode of operation:
- the first plurality of weight values is received via a second portion of the plurality of inputs different than the first portion of the plurality of inputs, wherein the second portion of the plurality of inputs are coupled to a second portion of programmable logic;
- and
- the second plurality of weight values is received via the first portion of the plurality of inputs;
- and
- a plurality of multipliers configurable to simultaneously multiply each respective weight value of the first plurality of weight values by a respective weight value of the second plurality of weight values.
6 more elements
An integrated circuit device, comprising:
- one or more digital signal processing (DSP) blocks, each of the one or more DSP blocks comprising:
- a plurality of inputs configurable to receive a first plurality of weight values and a second plurality of weight values, wherein:
- in a first mode of operation, the first plurality of weight values and the second plurality of weight values are received via a first portion of the plurality of inputs coupled to a first portion of programmable logic;
- and
- in a second mode of operation:
- the first plurality of weight values is received via a second portion of the plurality of inputs different than the first portion of the plurality of inputs, wherein the second portion of the plurality of inputs are coupled to a second portion of programmable logic;
- and
- the second plurality of weight values is received via the first portion of the plurality of inputs;
- and
- a plurality of multipliers configurable to simultaneously multiply each respective value of the first plurality of weight values by a respective value of the second plurality of weight values.
7 more elements
A system comprising:
- a first integrated circuit device comprising:
- programmable logic;
- a first digital signal processing (DSP) block;
- and
- a second DSP block communicatively coupled to the first DSP block, wherein the second DSP block comprises:
- a plurality of inputs configurable to receive a first plurality of weight values and a second plurality of weight values, wherein:
- in a first mode of operation, the first plurality of weight values and the second plurality of weight values are received via a first portion of the plurality of inputs coupled to a first portion of the programmable logic;
- and
- in a second mode of operation:
- the first plurality of weight values is received via a second portion of the plurality of inputs different than the first portion of the plurality of inputs, wherein the second portion of the plurality of inputs are coupled to a second portion of the programmable logic;
- and
- the second plurality of weight values is received via the first portion of the plurality of inputs;
- and
- a plurality of multipliers configurable to simultaneously multiply each respective value of the first plurality of weight values by a respective value of the second plurality of weight values.
11 more elements
Dependencies are inferred from the claim text.