Apparatus and methods related to microcode instructions indicating instruction types
OwnerShawn Rosti, Timothy P. Finkbeinerinventors
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Abstract
The present disclosure includes apparatuses and methods related to microcode instructions indicating instruction types. One example apparatus comprises a memory storing a set of microcode instructions. Each microcode instruction of the set can comprise a first field comprising a number of control data units, and a second field comprising a number of type select data units. Each microcode instruction of the set can have a particular instruction type defined by a value of the number of type select data units, and particular functions corresponding to the number of control data units are variable based on the particular instruction type.
Claims14
A processor in memory (PIM) device, comprising:
- one or more memory arrays;
- one or more controllers coupled with the one or more memory arrays, and configured to cause the PIM device to:
- obtain an instruction comprising a set of bits;
- determine a type of the instruction based at least in part on a first subset of the set of bits, the type corresponding to a respective subset of a plurality of processing operations at the PIM device;
- and
- parse a second subset of the set of bits according to a first format, wherein the first format of the second subset of the set of bits is based at least in part on the type of the instruction;
- and
- one or more compute components in communication with the one or more controllers and the one or more memory arrays, and configured to:
- execute a first processing operation of the respective subset of the plurality of processing operations in accordance with parsing the second subset of the set of bits.
A method for operating a processor in memory (PIM) device, comprising:
- obtaining, at one or more controllers of the PIM device, an instruction comprising a set of bits;
- determining, at the one or more controllers of the PIM device, a type of the instruction based at least in part on a first subset of the set of bits, the type corresponding to a respective subset of a plurality of processing operations at the PIM device;
- parsing, at the one or more controllers, a second subset of the set of bits according to a first format, wherein the first format of the second subset of the set of bits is based at least in part on the type of the instruction;
- and
- execute, at one or more compute components of the PIM device, a first processing operation of the respective subset of the plurality of processing operations in accordance with parsing the second subset of the set of bits.
Dependencies are inferred from the claim text.