Memory system

A method of controlling a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells, each of the plurality of memory cells being configured to store n-bit data, the n being an integer larger than or equal to three, the method comprising:

• in response to a first command, applying a first voltage to a first word line of the word lines, a second voltage to a second word line of the word Tines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells as first data, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third memory cell being connected in series with the second memory cell;
• and
• in response to a second command, applying a fourth voltage to the first word line, applying a fifth voltage to the second word line, and applying a sixth voltage to the third word line, wherein
• the n-bit data corresponds to a first through a 2n-th threshold voltage ranges,
• the (i+1)-th threshold voltage range is greater than the i-th threshold voltage range, the i being an integer larger than or equal to one and smaller than or equal to (2n−1),
• the first voltage is at least one of first through (2n−1)-th threshold voltages,
• the j-th threshold voltage is a boundary voltage between the j-th threshold voltage range and the (j+1) threshold voltage range, the j being an integer larger than or equal to one and smaller than or equal to (2n−1), and
• each of the second through the sixth voltages is larger than the (2n−1)-th threshold voltage.