Seamlessly integrated microcontroller chip
AssigneeAyDeeKay LLC
InventorScott David Kee
Life of this patent
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Abstract
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
Claims20
A system, comprising:
- a first die with a central processing unit (CPU) and a first bridge;
- a second die with a second bridge, wherein the second die comprises a second CPU unrelated to the first bridge and the second bridge;
- and
- die-to-die interconnects electrically coupled to the first bridge and the second bridge, wherein the die-to-die interconnects comprise fewer signal lines than a first bus in the first die and a second bus in the second die,
- wherein the first bridge and the second bridge are configured to mask existence of the die-to-die interconnects, so that a function of the second die appears as though it is implemented on the first die to a master on the first die,
- wherein the first bridge and the second bridge are configured to sequentially use at least subsets of the die-to-die interconnects for command transport followed by selective data transport, and
- wherein the command transport is communicated in a single clock cycle.
A method of communicating between a first die with a first bridge and second die with a second bridge, comprising:
- receiving, at the first bridge, signals from a central processing unit (CPU) in the first die that correspond to a function of the second die;
- communicating, to the second bridge, the signals via die-to-die interconnects electrically coupled to the first bridge and the second bridge, wherein the first bridge and the second bridge sequentially use at least subsets of the die-to-die interconnects for command transport followed by selective data transport,
- wherein the die-to-die interconnects comprise fewer signal lines than a first bus in the first die and a second bus in the second die,
- wherein, when communicating the signals, the first bridge and the second bridge mask existence of the die-to-die interconnects, so that the function of the second die appears as though it is implemented on the first die to a master on the first die,
- wherein the second die comprises a second CPU unrelated to the first bridge and the second bridge, and
- wherein the command transport is communicated in a single clock cycle.
An electronic device, comprising:
- a first die with a central processing unit (CPU) and a first bridge;
- a second die with a second bridge, wherein the second die comprises a second CPU unrelated to the first bridge and the second bridge;
- and
- die-to-die interconnects electrically coupled to the first bridge and the second bridge, wherein the die-to-die interconnects comprise fewer signal lines than a first bus in the first die and a second bus in the second die,
- wherein the first bridge and the second bridge are configured to mask existence of the die-to-die interconnects, so that a function of the second die appears as though it is implemented on the first die to a master on the first die,
- wherein the first bridge and the second bridge are configured to sequentially use at least subsets of the die-to-die interconnects for command transport followed by selective data transport, and
- wherein the command transport is communicated in a single clock cycle.
Dependencies are inferred from the claim text.