Soft read operations with progressive data output

A memory chip controller comprising:

• one or more substrates;
• and
• logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
• trigger, via an initial request, a hard-read and a soft-read with respect to a memory cell in a memory device, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information;
• conduct a first error correction on the hard-bit information;
• and
• issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful.

A computing system comprising:

• a memory chip controller including first logic to:
• trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information,
• conduct a first error correction on the hard-bit information, and
• issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful;
• and
• a memory device including a plurality of memory cells and second logic to:
• conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request,
• send the hard-bit information to the controller;
• and
• withhold at least the second soft-bit information from the controller until the subsequent request is received.