Back to results
US 12,339,741 B2Granted
Bit efficient memory error correcting coding and decoding scheme
AssigneeGoogle Inc.
InventorsFabrice Aidan, Evgeni Krimer
Life of this patent
Estimating the term…
Abstract
Aspects of the disclosed technology include techniques and mechanisms for an efficient error correction coding scheme that can detect and correct data errors that may occur in a memory. In general, the scheme comprises segmenting the data that would be transferred as part of a data request into different parts and applying error correction codes to the separate parts.
Claims20
A method for encoding data associated with a request access for one or more DRAMs, comprising:
- segmenting a number of beats defined for a burst access to the one or more DRAMs into at least a first set of beats and a second set of beats;
- defining a first set of error correction code (ECC) for a first set of data associated with the first set of beats;
- and
- defining a second set of ECC for a second set of data associated with the second set of beats;
- wherein one of the first set of ECC comprises a first set of symbols, each symbol of the first set being associated with the first set of beats,
- wherein one of the second set of ECC comprises a second set of symbols, each symbol of the second set of symbols being associated with the second set of beats, wherein the first set of symbols comprises a different number of symbols than the second set of symbols and an error associated with the second set of ECC is correctable using information of the first set of ECC, and wherein the second set of ECC comprises one or more symbols used for storing metadata, the metadata being associated with a memory tag extension.
3 more elements
A memory system, comprising:
- one or more DRAMs;
- and
- a memory controller communicatively coupled to the one or more DRAMs, the memory controller having logic that implements the following function in response to a request access to the one or more DRAMs:
- segment a number of beats defined for a burst access to the one or more DRAMs in at least a first set of beats and a second set of beats;
- define a first set of error correction code (ECC) for a first set of data associated with the first set of beats;
- define a second set of ECC for a second set of data associated with the second set of beats;
- wherein one of the first set of ECC comprises a first set of symbols, each symbol of the first set being associated with the first set of beats,
- wherein one of the second set of ECC comprises a second set of symbols, each symbol of the second set of symbols being associated with the second set of beats, wherein the first set of symbols comprises a different number of symbols than the second set of symbols and an error associated with the second set of ECC is correctable using information of the first set of ECC, and wherein the second set of ECC comprises one or more symbols used for storing metadata, the metadata being associated with a memory tag extension.
5 more elements
Dependencies are inferred from the claim text.