Method and chip for cyclic code encoding, circuit component, and electronic device
AssigneeHuawei Technologies Co., Ltd.
InventorsLiang Li, Chun Yuan, Yuchun Lu, Lin Ma, Yongzhi Liu
Life of this patent
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Abstract
A method for cyclic code encoding includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence; generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols; and generating the (N−K) parity symbols based on the first parity sequence and the second parity sequence.
Claims27
A method comprising:
- generating, based on a first symbol sequence related to a first part of K payload symbols of a first cyclic code, a first parity sequence corresponding to the first symbol sequence, wherein K is an integer greater than 1;
- generating, based on a second symbol sequence related to a second part of the K payload symbols, a second parity sequence corresponding to the second symbol sequence, wherein the first part is different from the second part;
- and
- generating (N−K) parity symbols based on the first parity sequence and the second parity sequence,
- wherein N is an integer greater than K.
A chip comprising:
- a first encoder configured to generate, based on a first symbol sequence related to a first part of K payload symbols of a first cyclic code, a first parity sequence corresponding to the first symbol sequence, wherein K is an integer greater than 1;
- a second encoder configured to generate, based on a second symbol sequence related to a second part of the K payload symbols, a second parity sequence corresponding to the second symbol sequence, wherein the first part is different from the second part;
- and
- a combiner configured to generate the (N−K) parity symbols based on the first parity sequence and the second parity sequence,
- wherein N is an integer greater than K.
A circuit component comprising:
- a circuit board;
- and
- a chip mounted on the circuit board and comprising:
- a first encoder configured to generate, based on a first symbol sequence related to a first part of K payload symbols of a first cyclic code, a first parity sequence corresponding to the first symbol sequence, wherein K is an integer greater than 1;
- a second encoder configured to generate, based on a second symbol sequence related to a second part of the K payload symbols, a second parity sequence corresponding to the second symbol sequence, wherein the first part is different from the second part;
- and
- a combiner configured to generate the (N−K) parity symbols based on the first parity sequence and the second parity sequence,
- wherein N is an integer greater than K.
Dependencies are inferred from the claim text.