Method of failure analysis for defect locations

A failure analysis method for locating a defect position, comprising following steps:

• step 1, providing a chip sample having a metal layer, wherein the metal layer has an open circuit defect;
• step 2, delaminating the chip sample to expose a top surface of the metal layer having the open circuit defect;
• step 3, depositing a metal conductive layer on the metal layer of the chip sample;
• step 4, removing a portion of the metal conductive layer from a top surface the metal layer to expose the metal layer;
• step 5, depositing a non-conductive protective layer to cover the exposed metal layer and any remaining portions of the metal conductive layer of the chip sample;
• step 6, preparing a TEM (Transmission Electron Microscopy) slice sample from the chip sample, wherein the TEM slice sample comprises the metal layer, the remaining portions of the metal conductive layer, and the non-conductive protective layer;
• step 7, performing a VC (voltage contrast) analysis on the TEM slice sample to determine the defect position of the open circuit defect;
• and
• step 8, analyzing the defect position of the open circuit defect on the TEM slice sample.