Ferroelectric semiconductor device and method

A device comprising:

• an isolation region over a substrate;
• a semiconductor fin adjacent the isolation region, the semiconductor fin having a first top surface and first sidewalls above a second top surface of the isolation region;
• a crystalline gate dielectric layer on the first top surface of the semiconductor fin, the first sidewalls of the semiconductor fin, and the second top surface of the isolation region, the crystalline gate dielectric layer having a first crystallinity adjacent to the first top surface of the semiconductor fin and a second crystallinity adjacent to the second top surface of the isolation region, the first crystallinity being different from the second crystallinity;
• and
• a gate electrode over the crystalline gate dielectric layer.

A device comprising:

• a semiconductor fin extending from a substrate;
• a source/drain region in the semiconductor fin;
• a gate spacer adjacent the source/drain region;
• a gate dielectric layer adjacent the gate spacer and disposed over a channel region of the semiconductor fin, wherein the gate dielectric layer comprises a coercive field gradient extending along sidewalls of the semiconductor fin from a top of the semiconductor fin to a bottom of the semiconductor fin;
• and
• a gate electrode over the gate dielectric layer.