Threshold-based min-sum algorithm to lower the error floors of quantized low-density parity-check decoders

A method for lowering an error floor of a low-density parity-check (“LDPC”) decoder chip, thereby improving bit-error-rate and/or frame-error-rate performance of the LDPC decoder chip, the method comprising:

• for messages passed from a check node to a variable node, computing a check node log-likelihood ratio within the LDPC decoder chip by passing quantized messages from a first processing unit on the LDPC decoder chip to a second processing unit on the LDPC decoder chip, wherein a plurality of check nodes are connected to a variable node and wherein a variable node is connected to at least one of the plurality of check nodes, and wherein the connections are specified by a parity-check matrix of an LDPC code, wherein computing further comprises:
• comparing a value associated with a set of variable node log-likelihood ratio magnitudes with a threshold, wherein the input variable node log-likelihood ratio magnitudes are connected to a check node;
• based on the results of the comparison, determining whether to apply a reduction to a check node log-likelihood ratio magnitude or not to apply a reduction to the check node log-likelihood ratio magnitude;
• applying a reduction to the check node log-likelihood ratio magnitude in instances when the determining step determines that a reduction should be applied;
• and
• not applying a reduction to the check node log-likelihood ratio magnitude in instances when the determining step determines that a reduction should not be applied.