Digital frequency synthesizer

A method, comprising:

• receiving, by a first delay-locked loop (DLL) of a digital frequency synthesizer, a reference clock signal;
• generating, by the first DLL, a first plurality of delayed clock signals that are time-delayed versions of the reference clock signal;
• executing, by a clock divider of the digital frequency synthesizer, an integer-division operation on a first delayed clock signal of the first plurality of delayed clock signals to generate an integer-divided clock signal;
• generating, by control circuitry of the digital frequency synthesizer, based on the integer-divided clock signal, fractional data that enables a fractional division associated with the digital frequency synthesizer;
• selecting, by a first clock selector of the digital frequency synthesizer, based on the fractional data, one of the first plurality of delayed clock signals as a first DLL clock signal;
• generating, by a first output delay chain of the digital frequency synthesizer, a second plurality of delayed clock signals that are time-delayed versions of the first DLL clock signal;
• selecting, by a second clock selector of the digital frequency synthesizer, based on the fractional data, one of the second plurality of delayed clock signals as a first selected clock signal;
• adjusting, by a fractional clock generator of the digital frequency synthesizer, the integer-divided clock signal based on the first selected clock signal;
• and
• generating, by the fractional clock generator, a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.