Power management integrated circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsHyun Seok Nam, Jin Gyu Kang, Jeong Woon Kong, Yong Seong Roh
Life of this patent
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Abstract
A power management integrated circuit including: a clock generator that generates an input clock; a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter; a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter; and a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter, wherein the first phase, the second phase and the third phase have different phases from each other.
Claims20
A power management integrated circuit, comprising:
- a clock generator that generates an input clock;
- a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter;
- a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter;
- and
- a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter,
- wherein the input clock input to the first phase delay controller, the second phase delay controller, and the third phase delay controller has the same phase,
- wherein the first phase, the second phase and the third phase have different phases from each other,
- wherein the first to third phase delay controllers output the first to third supply clocks based on different first, second and third selection signals from each other, wherein the first, second and third selection signals are separately provided.
A power management integrated circuit, comprising:
- a clock generator that generates an input clock;
- a digital logic circuit that generates first and second delay signals;
- a first phase delay controller that delays the input clock by a first phase according to the first delay signal and outputs a first supply clock to a first switching converter;
- and
- a second phase delay controller that delays the input clock by a second phase according to the second delay signal and outputs a second supply clock to a second switching converter,
- wherein the first supply clock and the second supply clock are adjusted by the first and second phase delay controllers.
A power management integrated circuit, comprising:
- a first phase delay controller that adaptively delays an input clock by a first phase to generate a first supply clock;
- a first switching converter that performs a voltage conversion based on the first supply clock;
- a second phase delay controller that adaptively delays the input clock by a second phase to generate a second supply clock;
- and
- a second switching converter that performs voltage conversion based on the second clock supply,
- wherein the input clock input to the first phase delay controller, and the second phase delay controller has the same phase,
- wherein the first and second phase delay controllers output the first and second supply clocks based on different first and second selection signals from each other, wherein the first and second selection signals are separately provided.
Dependencies are inferred from the claim text.