Ternary logic element and ternary logic system including same

A ternary logic element comprising:

• a semiconductor substrate including any one of a hole barrier material and an electron barrier material;
• a semiconductor layer which is formed on the semiconductor substrate and which includes a first semiconductor portion, a second semiconductor portion extending from the first semiconductor portion, a third semiconductor portion extending from the second semiconductor portion, a fourth semiconductor portion extending from the third semiconductor portion, and a fifth semiconductor portion extending from the fourth semiconductor portion;
• an insulating portion which is disposed on the semiconductor layer and overlaps the second semiconductor portion and the fourth semiconductor portion;
• and
• a control electrode which is disposed on the insulating portion and overlaps the second semiconductor portion,
• wherein the first semiconductor portion, the third semiconductor portion, and the fifth semiconductor portion are each doped with any one of an n-type dopant and a p-type dopant, and the second semiconductor portion and the fourth semiconductor portion are each doped with the other type of dopant.

A ternary logic system comprising:

• a plurality of electronic elements;
• and
• a ternary logic element,
• wherein the ternary logic element includes:
• a transistor including a channel layer containing silicon, an input electrode, an output electrode, and a control electrode;
• and
• a switching element which includes an emitter, a base extending from the emitter, and a collector extending from the base and in which any one of the emitter and the collector is electrically connected to the channel layer and is connected to the transistor in series,
• each of the emitter, the base, and the collector includes silicon,
• each of the emitter and the collector is doped with any one of an n-type dopant and a p-type dopant, and the base is doped with the other type of dopant,
• a first portion and a second portion spaced apart from the first portion of the channel layer are each doped with the one type of dopant, a third portion is doped with the other type of dopant, and the first portion and the second portion are in contact with the input electrode and the output electrode, respectively,
• when a first control voltage is applied to the control electrode, a first voltage is output,
• when a second control voltage different from the first control voltage is applied to the control electrode, a second voltage different from the first voltage is output, and
• when a third control voltage different from the first control voltage and the second control voltage is applied to the control electrode, a third voltage different from the first voltage and the second voltage is output.