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US 12,334,872 B2Granted
Data driving circuit and display including the same
AssigneeLx Semicon Co., Ltd.
InventorsYong Sung Ahn, Ji Won Kim, Hyo Joong Kim, Kyung Min Shin, Kyu Tae Lee, Ha Rim Choi
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to an offset elimination operation of an internal operational amplifier of a data driving circuit and relates to a technique that applies different offset elimination methods for each position of an operational amplifier.
Claims20
A gamma voltage generation circuit comprising:
- a first multiplexer configured to select and supply with a voltage between a maximum reference voltage and a minimum reference voltage through a first resistor string;
- a second multiplexer configured to select and supply with a voltage between a maximum reference voltage and a minimum reference voltage through the first resistor string;
- a second resistor string;
- a first operational amplifier circuit connected to an uppermost end of the second resistor string and configured to output a first voltage corresponding to a highest voltage of the second resistor string based on the voltage received from the first multiplexer;
- a second operational amplifier circuit connected to a lowest end of the second resistor string and configured to output a second voltage corresponding to a lowest voltage of the second resistor string based on the voltage received from the second multiplexer;
- and
- a third operational amplifier circuit connected to a node of the second resistor string and configured to divide the first voltage and the second voltage and to output a third voltage,
- wherein the third operational amplifier circuit includes a first offset elimination circuit that is configured to eliminate an offset voltage through charging and discharging of a capacitor, and
- the first operational amplifier circuit and the second operational amplifier circuit are configured to eliminate an offset voltage in a manner different from that of the third operational amplifier circuit by a chopping method.
6 more elements
A data driving circuit comprising:
- a data voltage generation circuit configured to supply a data voltage to a pixel through a data line;
- and
- a gamma reference voltage generation circuit configured to distribute a power supply voltage formed at both ends of a resistor string to generate a gamma reference voltage and supply the gamma reference voltage to the pixel through the data line,
- wherein the gamma reference voltage generation circuit includes:
- a first multiplexer configured to select and supply with a voltage between a maximum reference voltage and a minimum reference voltage through a first resistor string;
- a second multiplexer configured to select and supply with a voltage between a maximum reference voltage and a minimum reference voltage through the first resistor string;
- a second resistor string;
- a first operational amplifier circuit connected to a first end of the second resistor string;
- a second operational amplifier circuit connected to a second end of the second resistor string;
- and
- a third operational amplifier circuit connected to a node of the second resistor string,
- wherein the first operational amplifier circuit and the second operational amplifier circuit are configured to eliminate an offset voltage of an internal operational amplifier in a manner different from that of the third operational amplifier circuit, and
- the first operational amplifier circuit and the second operational amplifier circuit are configured to eliminate the offset voltage by operation of a pair of switches that alternately change connection of input and output terminals.
10 more elements
A method of eliminating an offset comprising:
- eliminating an offset voltage of a first operational amplifier circuit connected to a first end of a first resistor string and outputting a first gamma reference voltage;
- eliminating an offset voltage of a second operational amplifier circuit connected to a second end of the first resistor string and outputting a second gamma reference voltage;
- and
- eliminating an offset voltage of a third operational amplifier circuit connected to a node of the first resistor string and outputting a third gamma reference voltage;
- selecting and supplying, by a first multiplexer, with a voltage between a maximum reference voltage and a minimum reference voltage through a second resistor string;
- and
- selecting and supplying, by a second multiplexer, with a voltage between a maximum reference voltage and a minimum reference voltage through the second resistor string,
- wherein the third operational amplifier circuit includes a first offset elimination circuit connected in parallel, and
- the first or second operational amplifier circuit includes a third offset elimination circuit that independently performs an offset elimination operation different from that of the first offset elimination circuit.
6 more elements
Dependencies are inferred from the claim text.