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US 12,334,128 B2Granted
Ferroelectric memory circuit and reading method thereof
AssigneeFerroelectric Memory GmbH
InventorsMarko Noack, Georgi Kuzmanov
Life of this patent
Estimating the term…
Abstract
A ferroelectric memory circuit (100) includes: a memory cell (102), wherein a memory state (102s) of the memory cell (102) is switchable between a first memory state and a second memory state, the memory cell (102) further configured to output an electrical current (101) in response to receiving a readout voltage (103); and a sense circuit (104) configured to output an output voltage (105) based on the result of integrating the electrical current (101) output by the memory cell (102), wherein the output voltage (105) represents whether the memory state (102s) is the first memory state or the second memory state.
Claims15
A memory cell circuit, comprising:
- a memory cell, wherein a memory state of the memory cell is switchable between a first memory state and a second memory state, the memory cell further configured to output an electrical current in response to receiving a readout voltage;
- and
- a sense circuit configured to output an output voltage based on the electrical current output by the memory cell, wherein the output voltage represents whether the memory state is the first memory state or the second memory state, wherein the sense circuit comprises a single-input inverter and an integrating capacitor, wherein the integrating capacitor couples an input node of the single-input inverter to an output of the single-input inverter that inverts signals as between the input node and the output,
- wherein the single-input inverter comprises a first transistor pair cascaded with a second transistor pair, wherein the input node comprises connected gates of a first transistor of the first transistor pair and of a first transistor of the second transistor pair, wherein the output of the single-input inverter is connected between a second transistor of the first transistor pair cascaded with a second transistor of the second transistor pair, wherein a gate of the second transistor of the first transistor pair is connected to a first control terminal that is separate from the input node, wherein a gate of the second transistor of the second transistor pair is connected to a second control terminal that is separate from the input node,
- wherein the first transistor of the first transistor pair is connected to a supply voltage and remains connected to the supply voltage even when the second transistor of the first transistor pair is switched off, wherein the first transistor of the second transistor pair is connected to a reference voltage and remains connected to the reference voltage when the second transistor of the second transistor pair is switched off.
2 more elements
A memory cell circuit, comprising:
- a set of memory cells, a first control line connecting the memory cells of the set of memory cells;
- a set of second control lines, each second control being connected to a respective memory cell of the set of memory cells,
- wherein a memory state of each of the memory cell is switchable between a first memory state and a second memory state, the memory cell further configured to output an electrical current via the first control line in response to receiving a readout voltage via one of the second control lines;
- and
- a sense circuit configured to output an output voltage based on the electrical current output by the memory cell, wherein the output voltage represents whether the memory state is the first memory state or the second memory state, wherein the sense circuit comprises a single-input inverter and an integrating capacitor, wherein the integrating capacitor couples an input the of the single-input inverter to an output of the single-input inverter,
- wherein the single-input inverter inverts signals as between the input node and the output, wherein the single-input inverter comprises a first transistor pair cascaded with a second transistor pair, wherein the input node comprises connected gates of a first transistor of the first transistor pair and of a first transistor of the second transistor pair, wherein the output of the single-input inverter is connected between a second transistor of the first transistor pair cascaded with a second transistor of the second transistor pair, wherein a gate of the second transistor of the first transistor pair is connected to a first control terminal that is separate from the input node, wherein a gate of the second transistor of the second transistor pair is connected to a second control terminal that is separate from the input node,
- wherein the first transistor of the first transistor pair is connected to a supply voltage and remains connected to the supply voltage even when the second transistor of the first transistor pair is switched off, wherein the first transistor of the second transistor pair is connected to a reference voltage and remains connected to the reference voltage when the second transistor of the second transistor pair is switched off.
4 more elements
Dependencies are inferred from the claim text.