# US 12,333,305 B2 · Delayed cache writeback instructions for improved data sharing in manycore processors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,333,305 B2 - Document ID: US12333305B2 - Status: Granted - Kind: B2 - Application number: 17/033,770 - Filed: 2020-09-26 - Published: 2022-03-31 - Granted: 2025-06-17 - Earliest claimed: 2020-09-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Wim Heirman; Stijn Eyerman; Ibrahim Hur - Web page: https://patentgrep.com/patent/US12333305B2 ## CPC - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory} - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 2212/1021: Hit rate improvement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and apparatus relating to one or more delayed cache writeback instructions for improved data sharing in manycore processors are described. In an embodiment, a delayed cache writeback instruction causes a cache block in a modified state in a Level 1 (L1) cache of a first core of a plurality of cores of a multi-core processor to a Modified write back (M.wb) state. The M.wb state causes the cache block to be written back to LLC upon eviction of the cache block from the L1 cache. Other embodiments are also disclosed and claimed. ## Claims ### Claim 1 An apparatus comprising: a Last Level Cache (LLC) coupled to a plurality of cores of a multi-core processor, the LLC to store data accessible by the plurality of the cores; decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to include a field to indicate a location that is to store a cache block address and an opcode to indicate that execution circuitry is to cause a state of a cache block at the cache block address to be changed to a modified writeback state, wherein the cache block in the modified writeback state is to indicate that the cache block is stored to both the LLC and a Level 2 (L2) cache upon eviction of the cache block from a Level 1 (L1) cache; and execution circuitry to execute the decoded instance of the single instruction according to the opcode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the cache block is to be kept in a shared state in the L2 cache of a first core from the plurality of cores. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the cache block comprises one or more cache lines. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the cache block is to move into a replacement position in the L1 cache for preferential selection for replacement. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the field to indicate a location that is to store a cache block address is to identify a register. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the multi-core processor, the LLC, and the L1 cache are on a single integrated circuit die. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the multi-core processor comprises a Graphics Processing Unit (GPU). ### Claim 8 (depends on 1) The apparatus of claim 1, further comprising a performance counter to count a number of local write hits on cache lines in the modified writeback state. ### Claim 9 (depends on 1) The apparatus of claim 1, further comprising a performance counter to count a number of hits caused by a request from a remote core on cache lines in the modified writeback state. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the L2 cache is private to a core from the plurality of cores. ### Claim 11 One or more non-transitory computer-readable media comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to: decode an instance of a single instruction, the instance of the single instruction to include a field to indicate a location that is to store a cache block address and an opcode to indicate that execution circuitry is to cause a state of a cache block at the cache block address to be changed to a modified writeback state, wherein the cache block in the modified writeback state is to indicate that the cache block is stored to both a Last Level Cache (LLC) and a Level 2 (L2) cache upon eviction of the cache block from a Level 1 (L1) cache; and execute the decoded instance of the single instruction according to the opcode. ### Claim 12 (depends on 11) The one or more non-transitory computer-readable media of claim 11, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to move the cache block into a replacement position in the L1 cache for preferential selection for replacement. ### Claim 13 (depends on 11) The one or more non-transitory computer-readable media of claim 11, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to keep the cache block in a shared state in the L2 cache of a first core from a plurality of cores. ### Claim 14 (depends on 11) The one or more non-transitory computer-readable media of claim 11, further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to update a performance counter to count a number of local write hits on cache lines in the modified writeback state.