Automatic test equipment architecture providing odd sector size support

An automatic test equipment (ATE) apparatus comprising:

• a host bus adapter coupled to a load board between a host device tester and one or more devices under test;
• and
• one or more field programmable gate arrays (FPGAs) coupled to the load board;
• wherein the one or more devices under test support an odd sector size or non-standard sector size;
• wherein the host device tester executes an operating system that does not support the odd sector size or non-standard sector size;
• and
• wherein the host bus adapter is configured to translate memory accesses received from the host device tester using a first communication protocol interface to memory accesses using a second communication protocol interface to send to the one or more devices under test;
• and
• wherein the one or more field programmable gate arrays (FPGAs) is configured to generate at a hardware level repeatable test patterns sized to fit the odd sector size or non-standard sector size of the one or more devices under test.

A method of accessing memory of one or more devices under test comprising:

• receiving, by a load board, a memory access from a host device tester on a first communication protocol interface, wherein an operating system of the host device tester does not support an odd sector sizes or a non-standard sector sizes;
• passing, by the load board, the memory access from the host device tester to a host bus adapter and a field programmable gate array;
• translating, by the host bus adapter, the memory access of a first communication protocol to the memory access of a second communication protocol:
• generating, by the field programmable gate array at a hardware level, tester patterns of the memory access for an odd sector size or non-standard sector size of the one or more devices under test;
• and
• sending, by the host bus adapter, the odd sector size or non-standard sector size memory access including the tester patterns to the one or more devices under test on a second communication protocol interface, wherein the one or more devices under test support the odd sector size or the non-standard sector size memory access.