Substrate-less silicon controlled rectifier (SCR) integrated circuit structures

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including a substrate-less integrated circuit structure, comprising:
• a first fin portion and a second fin portion that meet at a junction;
• a plurality of gate structures over the first fin portion and the second fin portion;
• and
• a plurality of P-type epitaxial structures and N-type epitaxial structures between corresponding adjacent ones of the plurality of gate structures, wherein pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures, and a corresponding one or more open locations is between neighboring pairs of the P-type epitaxial structures and pairs of the N-type epitaxial structures, wherein each of the one or more open locations is directly between corresponding ones of the plurality of gate structures.

A substrate-less integrated circuit structure, comprising:

• a first fin portion and a second fin portion that meet at a junction;
• a plurality of gate structures over the first fin portion and the second fin portion;
• a plurality of P-type epitaxial structures and N-type epitaxial structures between corresponding adjacent ones of the plurality of gate structures, wherein a pair of the P-type epitaxial structures is over the second fin portion, and a pair of the N-type epitaxial structures is over the first fin portion;
• an open location over the junction between the first fin portion and the second fin portion, wherein the open location is directly between corresponding ones of the plurality of gate structures;
• a first backside metallization structure coupled to a bottom of the first fin portion;
• and
• a second backside metallization structure coupled to a bottom of the second fin portion.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including a substrate-less integrated circuit structure, comprising:
• a first fin portion and a second fin portion that meet at a junction;
• a plurality of gate structures over the first fin portion and the second fin portion;
• a plurality of P-type epitaxial structures and N-type epitaxial structures between corresponding adjacent ones of the plurality of gate structures, wherein a pair of the P-type epitaxial structures is over the second fin portion, and a pair of the N-type epitaxial structures is over the first fin portion;
• an open location over the junction between the first fin portion and the second fin portion, wherein the open location is directly between corresponding ones of the plurality of gate structures;
• a first backside metallization structure coupled to a bottom of the first fin portion;
• and
• a second backside metallization structure coupled to a bottom of the second fin portion of the P-type epitaxial structures and pairs of the N-type epitaxial structures.