High writing rate antifuse array

An antifuse array, comprising

• a plurality of parallel bit lines, extending along a first direction and including a first bit line and a second bit line, which neighbor each other;
• a plurality of parallel word lines, extending along a second direction, vertical to the plurality of bit lines, and including a first word line, wherein the second direction is different from the first direction;
• a plurality of parallel select lines, extending along the second direction, parallel to the word lines, and including a first select line;
• and
• at least one sub-memory array, including a first antifuse memory cell and a second antifuse memory cell, wherein the first antifuse memory cell includes a first antifuse transistor connected with the first bit line, and a first selection transistor cascaded to the first antifuse transistor and connected with the first word line and the first select line, and wherein the second antifuse memory cell includes a second antifuse transistor connected with the second bit line, and a second selection transistor cascaded to the second antifuse transistor and connected with the first word line and the first select line, and wherein the first antifuse memory cell and the second antifuse memory cell neighbor each other in the second direction and are disposed between the first bit line and the second bit line, and
• wherein each of the first antifuse transistor and the second antifuse transistor includes a first gate dielectric layer and an antifuse gate;
• the antifuse gate has at least one sharp corner overlapping the first gate dielectric layer;
• each of the first selection transistor and the second selection transistor includes a second gate dielectric layer;
• the second gate dielectric layers are directly connected with each other;
• wherein a first channel is formed under the antifuse gate;
• the first selection transistor and the second selection transistor share a second channel;
• a width of the second channel is larger than a width of the first channel;
• the first antifuse memory cell and the second antifuse memory cell are disposed between the first bit line and the second bit line;
• the first gate dielectric layer and the second gate dielectric layer are connected to each other.