Sampling circuit, analog-to-digital converter circuit, and semiconductor integrated circuit

An analog-to-digital converter circuit configured to repeatedly perform a series of operations including a reset operation, a sampling operation, and a successive approximation operation and convert an analog input voltage into a first bit-number digital code, the analog-to-digital converter circuit comprising:

• a plurality of first capacitors, each of the first capacitors including a first terminal and a second terminal;
• a plurality of second capacitors, each of the second capacitors including a third terminal and a fourth terminal;
• a first top node configured to be connected to the second terminals of the plurality of first capacitors;
• a second top node configured to be connected to the fourth terminals of the plurality of second capacitors;
• a first input node configured to receive a first input voltage that is one of a differential input voltage;
• a second input node configured to receive a second input voltage that is the other of the differential input voltage;
• a first switch circuit configured to be provided between the first input node and a first bottom node;
• a second switch circuit configured to be provided between the second input node and a second bottom node;
• a third switch circuit configured to be provided between the first bottom node and the second bottom node;
• a fourth switch circuit configured to be provided between the first top node and the second top node;
• a plurality of fifth switch circuits configured to connect the first terminals of the plurality of first capacitors to the first bottom node, a first reference voltage node, or a second reference voltage node respectively;
• a plurality of sixth switch circuits configured to connect the third terminals of the plurality of second capacitors to the second bottom node, the first reference voltage node, or the second reference voltage node respectively;
• a comparator configured to compare a voltage of the first top node and a voltage of the second top node;
• and
• a control circuit configured to control a plurality of the fifth switch circuits and a plurality of the sixth switch circuits based on an output signal of the comparator during the successive approximation operation, wherein
• during the reset operation, the first switch circuit and the second switch circuit are configured to be turned off, the third switch circuit and the fourth switch circuit are configured to be turned on, the plurality of fifth switch circuits are configured to connect the first terminals of the plurality of first capacitors to the first bottom node respectively, and the plurality of sixth switch circuits are configured to connect the third terminals of the plurality of second capacitors to the second bottom node respectively.

A semiconductor integrated circuit, comprising:

• an internal circuit configured to output an analog differential input voltage;
• and
• an analog-to-digital converter circuit configured to convert the differential input voltage into a first bit-number digital code, wherein
• the analog-to-digital converter circuit is configured to perform a series of operations including a reset operation, a sampling operation, and a successive approximation operation, the analog-to-digital converter circuit includes:
• a plurality of first capacitors, each of the first capacitors including a first terminal and a second terminal;
• a plurality of second capacitors, each of the second capacitors including a third terminal and a fourth terminal;
• a first top node configured to be connected to the second terminals of the plurality of first capacitors;
• a second top node configured to be connected to the fourth terminals of the plurality of second capacitors;
• a first input node configured to receive a first input voltage that is one of the differential input voltage;
• a second input node configured to receive a second input voltage that is the other of the differential input voltage;
• a first switch circuit configured to be provided between the first input node and a first bottom node;
• a second switch circuit configured to be provided between the second input node and a second bottom node;
• a third switch circuit configured to be provided between the first bottom node and the second bottom node;
• a fourth switch circuit configured to be provided between the first top node and the second top node;
• a plurality of fifth switch circuits configured to connect the first terminals of the plurality of first capacitors to the first bottom node, a first reference voltage node, or a second reference voltage node respectively;
• a plurality of sixth switch circuits configured to connect the third terminals of the plurality of second capacitors to the second bottom node, the first reference voltage node, or the second reference voltage node respectively;
• a comparator configured to compare a voltage of the first top node and a voltage of the second top node;
• and
• a control circuit configured to control the plurality of fifth switch circuits and the plurality of sixth switch circuits based on an output signal of the comparator during the successive approximation operation, and
• during the reset operation, the first switch circuit and the second switch circuit are configured to be turned on, the third switch circuit and the fourth switch circuit are configured to be turned off, the plurality of fifth switch circuits are configured to connect the first terminals of the plurality of first capacitors to the first bottom node respectively, and a plurality of the sixth switch circuits are configured to connect the third terminals of the plurality of second capacitors to the second bottom node respectively.