Apparatus and methods for local oscillator interface circuits with quadrature clock generation and phase correction

A method of clock processing, the method comprising:

• receiving, at a first pin of a semiconductor die, a non-inverted component of a differential input clock signal from an oscillator that is external to the semiconductor die;
• receiving, at a second pin of the semiconductor die, an inverted component of the differential input clock signal from the oscillator;
• processing the differential input clock signal using an oscillator interface circuit of the semiconductor die, the oscillator interface circuit including a first controllable resistor and a first controllable capacitor connected in series between the first pin and the second pin, and a second controllable resistor and a second controllable capacitor connected in series between the second pin and the first pin, wherein the first controllable resistor connects to the first controllable capacitor at a first node, and the second controllable resistor connects to the second controllable capacitor at a second node;
• generating a plurality of quadrature clock signals using a clock processing circuit having a non-inverted in-phase (I) input connected to the first pin, a non-inverted quadrature-phase (Q) input connected to the first node, an inverted Q input connected to the second node, and an inverted I input connected to the second pin;
• and
• converting a single-ended I signal from one of the first pin or the second pin to a differential I clock signal using a first single-ended to differential conversion circuit of the clock processing circuit, and converting a single-ended Q signal from one of the first node or the second node to a differential Q clock signal using a second single-ended to differential conversion circuit of the clock processing circuit.

A clock system comprising:

• an oscillator configured to provide a differential input clock signal;
• and
• a semiconductor die including a first pin configured to receive a non-inverted component of the differential input clock signal, a second pin configured to receive an inverted component of the differential input clock signal, and an oscillator interface circuit including a first controllable resistor and a first controllable capacitor connected in series between the first pin and the second pin, and a second controllable resistor and a second controllable capacitor connected in series between the second pin and the first pin, wherein the first controllable resistor connects to the first controllable capacitor at a first node, and the second controllable resistor connects to the second controllable capacitor at a second node, the semiconductor die further comprising a clock processing circuit having a non-inverted in-phase (I) input connected to the first pin, a non-inverted quadrature-phase (Q) input connected to the first node, an inverted Q input connected to the second node, and an inverted I input connected to the second pin, the clock processing circuit comprising a first single-ended to differential conversion circuit configured to convert a single-ended I signal from one of the first pin or the second pin to a differential I clock signal, and a second single-ended to differential conversion circuit configured to convert a single-ended Q signal from one of the first node or the second node to a differential Q clock signal.

A semiconductor die comprising:

• a first pin configured to receive a non-inverted component of a differential input clock signal from an oscillator external to the semiconductor die;
• a second pin configured to receive an inverted component of the differential input clock signal;
• an oscillator interface circuit comprising a first controllable resistor and a first controllable capacitor connected in series between the first pin and the second pin, and a second controllable resistor and a second controllable capacitor connected in series between the second pin and the first pin, wherein the first controllable resistor connects to the first controllable capacitor at a first node, and the second controllable resistor connects to the second controllable capacitor at a second node;
• and
• a clock processing circuit having a non-inverted in-phase (I) input connected to the first pin, a non-inverted quadrature-phase (Q) input connected to the first node, an inverted Q input connected to the second node, and an inverted I input connected to the second pin, wherein the non-inverted I input of the clock processing circuit is directly connected to a first end of the first controllable resistor, the non-inverted Q input of the clock processing circuit is directly connected to a second end of the first controllable resistor, the inverted I input of the clock processing circuit is directly connected to a first end of the second controllable resistor, and the inverted Q input of the clock processing circuit is directly connected to a second end of the second controllable resistor.