Semiconductor device

A semiconductor device comprising:

• a data receiving circuit configured to convert external stream data to internal data processable in the semiconductor device;
• a level detection circuit configured to validate a level detection signal when a value indicated in the internal data successes a threshold value;
• a ring buffer circuit configured to sequentially and cyclically store the internal data in a storage area set within a predetermined address range;
• a bus clock generation circuit configured to generate a bus clock;
• a data processing circuit configured to perform a data processing based on the internal data obtained from the ring buffer circuit, the data processing being performed by the bus clock;
• and
• a system controller circuit configured to selectively operates the bus clock generator during a period in which the level detection signal indicates a valid state,
• wherein the ring buffer circuit comprises:
• a write address generating circuit configured to operate with a core clock used to capture the external stream data and generate a cyclically changing write address;
• a storage circuit configured to operate with the core clock and accumulates the internal data in the area specified by the write address;
• a read address generator circuit configured to operate with the bus clock and generates a cyclically changing read address;
• and
• an address adjusting circuit that adjusts the difference between the read address and the write address to be less than the size of the predetermined address range at the timing of starting generation of the bus clock.