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US 12,327,599 B2Granted
Memory with scan chain testing of column redundancy logic and multiplexing
AssigneeQUALCOMM Incorporated
InventorsRahul Sahu, Sharad Kumar Gupta, Jung Pill Kim, Chulmin Jung, Jais Abraham
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Abstract
A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.
Claims14
A memory, comprising:
- a plurality of columns, each column including:
- a bit line;
- a complement bit line;
- a first read multiplexer transistor coupled to the bit line and having a read terminal;
- a second read multiplexer transistor coupled to the complement bit line and having a complement read terminal;
- a sense amplifier having a first input terminal coupled to the read terminal and a second input terminal coupled to the complement read terminal;
- a read column redundancy multiplexer having a first input terminal coupled to an output terminal of the sense amplifier and having a second input terminal coupled to a sense amplifier in an adjacent column;
- and
- a data output latch having an input terminal coupled to an output terminal of the read column redundancy multiplexer through a direct electrical connection.
6 more elements
Dependencies are inferred from the claim text.