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US 12,327,594 B2Granted
3D flash memory module chip and method of fabricating the same
AssigneeMacronix International Co., Ltd.
InventorsTeng-Hao Yeh, Hang-Ting Lue
Life of this patent
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Abstract
A 3D flash memory module chip includes a memory chip and a control chip. The memory chip includes a plurality of tiles and a plurality of heaters. The tiles each include a plurality of 3D flash memory structures. The heaters are disposed around the 3D flash memory structures of each of the tiles. The control chip is bonded with the memory chip to drive at least one of the heaters.
Claims15
A 3D flash memory module chip comprising:
- a memory chip comprising:
- a plurality of tiles each comprising a plurality of 3D flash memory structures;
- and
- a plurality of heaters disposed around the 3D flash memory structures of each of the tiles;
- and
- a control chip bonded with the memory chip to drive at least one of the heaters, wherein the control chip comprises:
- a plurality of driving rows each comprising:
- a second transistor located on a second substrate, wherein a source region of the second transistor is electrically connected to a global power supply;
- a first pad electrically connected to a drain region of the second transistor and electrically connected to a first end of one of the heaters;
- and
- a second pad that is grounded and is electrically connected to a second end of the one of the heaters.
8 more elements
A method of fabricating a 3D flash memory module chip, comprising:
- forming a memory chip, comprising:
- forming a plurality of tiles on a first substrate, wherein each of the tiles comprises a plurality of 3D flash memory structures;
- and
- forming a plurality of heaters around the 3D flash memory structures of each of the tiles;
- forming a control chip;
- and
- bonding the control chip and the memory chip, wherein the control chip is configured to drive the heaters,
- wherein the step of forming the control chip comprises:
- forming a plurality of driving rows, wherein formation of each of the driving rows comprises:
- forming a second transistor on a second substrate;
- forming a second interconnect structure on the second transistor, wherein a source region of the second transistor is electrically coupled to a global power supply via the second interconnect structure;
- forming a first pad on the second interconnect structure, wherein the first pad is electrically connected to a drain region of the second transistor via the second interconnect structure;
- forming a second pad on the second interconnect structure, wherein the second pad is electrically connected to ground via the second interconnect structure;
- electrically connecting the first pad to a first end of one of the heaters;
- and
- electrically connecting the second pad that to a second end of the one of the heaters.
13 more elements
Dependencies are inferred from the claim text.