Register, flop, and latch designs inlcuding ferroelectric and linear dielectrics

An integrated circuit chip comprising:

• memory circuitry comprising, a plurality of registers, a first register of the plurality of registers comprising:
• a first transmission gate comprising a first transistor connected between a first node and a second node, the first transistor having a gate terminal connected to a first clock node, the first clock node configured to receive a first clock signal;
• a first capacitor connected between the second node and a first voltage node, the first capacitor is a ferroelectric capacitor, wherein the first voltage node is configured to receive a second clock signal;
• second transmission gate comprising a second transistor connected between the second node and a third node, the second transistor having a gate terminal connected to the first clock node;
• and
• a second capacitor connected between the third node and a second voltage node;
• and
• memory controller circuitry coupled to the memory circuitry and configured to at least one of drive a first signal onto the first node to update the first register and receive a second signal from the third node to read a value of the first register.

A memory circuitry comprising:

• a first transmission gate connected between a first node and a second node, and configured to receive a first clock signal;
• a second transmission gate connected between the second node and a third node, and configured to receive the first clock signal;
• a third transmission gate connected between the third node and a fourth node, and configured to receive the first clock signal;
• a first capacitor connected between the second node and a first voltage node;
• a second capacitor connected between the third node and a second voltage node;
• and
• a third capacitor connected between the fourth node and a third voltage node.