Technologies for offload device fetching of address translations

A compute device comprising:

• a processor;
• a memory;
• an input/output memory management unit (IOMMU);
• an offload device;
• and
• one or more storage devices comprising a plurality of instructions stored thereon that, when executed by the processor, causes the processor to:
• determine a plurality of virtual memory addresses to be used by the offload device to execute a task;
• and
• send a translation fetch descriptor comprising an indication of the plurality of virtual memory addresses to the offload device,
• wherein the offload device, in response to receipt of the translation fetch descriptor, is to:
• send a request to the IOMMU for a physical address corresponding to individual virtual memory addresses of the plurality of virtual memory addresses;
• receive, for individual virtual memory addresses of the plurality of virtual memory addresses, a physical memory address;
• cache, for individual virtual memory addresses of the plurality of virtual memory addresses, the corresponding physical memory address in an address translation cache (ATC) of the offload device;
• and
• send, without reading from or writing to any of the physical addresses corresponding to the plurality of virtual memory addresses, an indication to the processor that the translation fetch descriptor has been processed,
• wherein the plurality of instructions further cause the processor to send a work descriptor to the offload device to execute the task, wherein the task to be executed by the offload device requires a read from or a write to individual virtual memory addresses of the plurality of virtual memory addresses,
• wherein the offload device is to:
• receive the work descriptor from the processor after the indication is sent to the processor that the translation fetch descriptor has been processed, wherein the plurality of virtual memory addresses indicated by the translation fetch descriptor correlates to the work descriptor;
• and
• perform the task identified in the work descriptor by performing direct memory access (DMA) operations to individual physical memory addresses corresponding to individual virtual memory addresses of the plurality of virtual memory addresses by accessing physical addresses stored in the ATC and without requesting address translation by the IOMMU during performance of the task.

One or more non-transitory computer-readable media comprising a plurality of instructions stored thereon that, when executed by a processor of a compute device, causes the processor to:

• determine a plurality of virtual memory addresses to be used by an offload device of the compute device to execute a task;
• send a translation fetch descriptor comprising an indication of the plurality of virtual memory addresses to the offload device to instruct the offload device to fetch physical addresses corresponding to the plurality of virtual addresses, wherein the offload device is to, in response to the translation fetch descriptor, cache, for individual virtual memory addresses of the plurality of virtual memory addresses, the corresponding physical memory address in an address translation cache (ATC) of the offload device;
• perform one or more operations after sending of the translation fetch descriptor;
• receive, from the offload device, an indication that the translation fetch descriptor has been processed;
• and
• send, after performance of the one or more operations, a work descriptor to the offload device to execute the task after performance of the one or more operations, wherein the task to be executed by the offload device requires a read from or a write to individual virtual memory addresses of the plurality of virtual memory addresses, wherein the offload device is to, in response to receipt of the work descriptor, perform the task identified in the work descriptor by performing direct memory access (DMA) operations to individual physical addresses corresponding to individual virtual memory addresses of the plurality of virtual memory addresses by accessing physical memory addresses stored in the ATC and without requesting address translation by an IOMMU during performance of the task.