Semiconductor device with modified access and associated methods and systems

A method, comprising:

• enabling a mode of a memory device based on one or more values of a mode register of the memory device, the mode associated with a first burst length of a plurality of burst lengths;
• retrieving first data from a memory array based at least in part on a read command;
• transmitting, at a time that is a number of clock cycles after the read command is received, the first data using one or more DQ pins and using the first burst length associated with the enabled mode based at least in part on the read command, the number of clock cycles based at least in part on latency information for the memory array;
• and
• transmitting second data following the first data using the one or more DQ pins, the second data comprising information calculated from the first data and used to detect errors in the first data.

A method, comprising:

• enabling a mode of a memory device based on one or more values of a mode register of the memory device, the mode associated with a first burst length of a plurality of burst lengths;
• retrieving first data from a memory array based at least in part on a read command;
• identifying at least one error in the first data;
• correcting, in accordance with an on-die error-correcting code (ECC) functionality, the at least one error in the first data;
• calculating information from the first data based at least in part on identifying and correcting the at least one error;
• transmitting, at a time that is a number of clock cycles after the read command is received, the first data using one or more DQ pins and using the first burst length associated with the enabled mode based at least in part on the read command, the number of clock cycles based at least in part on latency information for the memory array;
• and
• transmitting second data following the first data using the one or more DQ pins, the second data comprising the information calculated from the first data and used to detect errors in the first data.

A memory device, comprising:

• one or more memory arrays;
• and
• one or more controllers coupled with the one or more memory arrays, the one or more controllers operable to:
• enable a mode of a memory device based on one or more values of a mode register of the memory device, the mode associated with a first burst length of a plurality of burst lengths;
• correct, in accordance with an on-die error-correcting code (ECC) functionality of the memory device, at least one error in first data retrieved from a memory array of the one or more memory arrays, the first data retrieved based at least in part on a read command;
• transmit, based at least in part on the read command and at a time that is a number of clock cycles after the read command is received, the first data and using the first burst length associated with the enabled mode after correcting the at least one error, the number of clock cycles based at least in part on latency information for the memory array;
• generate, in accordance with the on-die ECC functionality of the memory device, a set of ECC bits for second data received via a write command;
• and
• write, based at least in part on the write command and after generating the set of ECC bits, the second data and the set of ECC bits to the one or more memory arrays.