Configurable microphone using internal clock changing

A circuit comprising:

• a clock divider having an input coupled to a clock signal input;
• a multiplexer having a first input coupled to an output of the clock divider, a second input coupled to the clock signal input, a third input coupled to a control signal input, and an output, wherein the multiplexer is configured to couple either of the first input and the second input to the output of the multiplexer according to a state of the control signal input;
• a signal processing circuit having an analog signal input, a clock input coupled to the output of the multiplexer, and a digital signal output comprising one or more output nodes;
• and
• a frequency converter coupled between the digital signal output of the signal processing circuit and a data stream output, wherein a conversion factor of the frequency converter is determined according to the state of the control signal input,
• wherein the signal processing circuit is configured to:
• in a first operational mode, convert an analog output of a microelectromechanical system (MEMS) into a first internal data stream having a first sampling rate derived from a clock frequency of an undivided clock signal and a first external data stream having the first sampling rate;
• transition from the first operational mode to a second operational mode without restarting the MEMS;
• in the second operational mode, convert the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and perform a sampling rate conversion of the second internal data stream to generate a second external data stream having the first sampling rate, wherein the second sampling rate is derived from a clock frequency of a divided clock signal;
• input the undivided clock signal into the first input of the multiplexer;
• input the undivided clock signal into the clock divider to generate the divided clock signal;
• input the divided clock signal into the second input of the multiplexer;
• and
• input a control signal to a control input of the multiplexer, the control signal indicating one of the first and second operational modes,
• wherein, in the first operational mode, the multiplexer couples the first input of the multiplexer to the output of the multiplexer, wherein, in the second operational mode, the multiplexer couples the second input of the multiplexer to the output of the multiplexer, and wherein the output of the multiplexer provides the undivided clock signal in the first operational mode and provides the divided clock signal in the second operational mode.

A microelectromechanical (MEMS) circuit in a single package comprising:

• a control signal input, a clock signal input, and a data stream output for providing a constant rate single bit output stream at one or more output nodes;
• a MEMS device;
• and
• a signal processing circuit coupled to the MEMS device, to the control signal input, to the clock signal input, and the data stream output, wherein the signal processing circuit is configured to:
• in a first operational mode, convert an analog output of the MEMS device into a first internal data stream having a first sampling rate derived from a clock frequency of an undivided clock signal and a first external data stream having the first sampling rate;
• transition from the first operational mode to a second operational mode without restarting the MEMS;
• and
• in the second operational mode, convert the analog output of the MEMS device into a second internal data stream having a second sampling rate different from the first sampling rate, and perform a sampling rate conversion of the second internal data stream to generate a second external data stream having the first sampling rate, wherein the second sampling rate is derived from a clock frequency of a divided clock signal.