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US 12,324,146 B2Granted
Vertical DRAM structure and method of formation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSai-Hooi Yeong, Bo-Feng Young, Chi On Chui
Life of this patent
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Abstract
Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.
Claims19
A method comprising:
- depositing a first insulating layer over a substrate;
- forming a bitline wiring in the first insulating layer, the bitline wiring having a first lengthwise direction;
- depositing a semiconductor material layer over the first insulating layer;
- patterning the semiconductor material layer into a plurality of pillars disposed along the bitline wiring;
- depositing a gate dielectric layer over the pillars;
- depositing a second insulating layer over the gate dielectric layer;
- and
- forming a capacitor directly over each pillar of the plurality of pillars.
5 more elements
A method comprising:
- forming an opening in a first insulating layer, the opening exposing an upper surface of a first vertical channel region of a first transistor, the first vertical channel region laterally surrounded by a gate dielectric and a gate electrode, the gate electrode spanning laterally to further surround a second vertical channel region of a second transistor;
- depositing a conformal second insulating layer in the opening over a conductive area of the first transistor;
- depositing a top electrode layer in order to fill a remainder of the opening, the top electrode layer extending over an upper surface of the first insulating layer;
- and
- separating the top electrode layer and second insulating layer to form a first capacitor over the first vertical channel region and a second capacitor over the second vertical channel region.
2 more elements
A method of forming a semiconductor structure, the method comprising:
- forming a bitline wiring in a first dielectric layer;
- a first semiconductor pillar disposed over and coupled to the bitline wiring, the bitline wiring extending in a first direction;
- forming a gate dielectric laterally surrounding the first semiconductor pillar;
- forming a gate electrode laterally surrounding the first semiconductor pillar, wherein the gate dielectric separates the gate electrode from the first semiconductor pillar, the gate electrode extending in a second direction perpendicular to the first direction in a plan view;
- forming a second dielectric layer over the gate electrode;
- and
- forming a capacitor in the second dielectric layer and disposed directly over the first semiconductor pillar.
4 more elements
Dependencies are inferred from the claim text.