Image output synchronization method and device
AssigneeAdlink Technology Inc.
InventorYu-Sheng Tseng
Life of this patent
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Abstract
An image output synchronization method, performed by a programmable logic circuit connected to an oscillator, includes: configuring a count value according to a designated frame rate and a frequency of the oscillator generating a count signal by each one of a plurality of frame controllers; generating a synchronization signal periodically and outputting the synchronization signal to the frame controllers by a clock generator; and performing a synchronization procedure on a camera by each one of the frame controllers when triggered by the synchronization signal every time, with the synchronization procedure including: triggered by the count signal of the oscillator to control a frame control signal outputted to the camera according to the count value and a width of the count signal.
Claims16
An image output synchronization method, performed by a programmable logic circuit connected to an oscillator, comprising:
- configuring a count value according to a designated frame rate and a frequency of the oscillator generating a count signal by each one of a plurality of frame controllers;
- generating a synchronization signal periodically and outputting the synchronization signal to the frame controllers by a clock generator;
- and
- performing a synchronization procedure on a camera by each one of the frame controllers when triggered by the synchronization signal every time, with the synchronization procedure comprising:
- triggered by the count signal of the oscillator to control a frame control signal outputted to the camera according to the count value and a width of the count signal,
- wherein controlling the frame control signal outputted to the camera according to the count value and the width of the count signal comprises:
- adding 1 to the count value;
- calculating a current clock width according to the count value and the width;
- determining whether the current clock width is smaller than a default clock width;
- making the frame control signal have a high potential if the current clock width is smaller than the default clock width;
- and
- making the frame control signal have a low potential if the current clock width is not smaller than the default clock width.
An image output synchronization device, comprising:
- a memory configured to store a configuration;
- and
- a programmable logic circuit connected to the memory, and configured to load the configuration to perform:
- configuring a count value according to a designated frame rate and a frequency of an oscillator generating a count signal by each one of a plurality of frame controllers;
- generating a synchronization signal periodically and outputting the synchronization signal to the frame controllers by a clock generator;
- and
- performing a synchronization procedure on a camera when triggered by the synchronization signal every time by each one of the frame controllers, with the synchronization procedure comprising:
- triggered by the count signal of the oscillator to control a frame control signal outputted to the camera according to the count value and a width of the count signal,
- wherein each one of the frame controllers performs controlling the frame control signal outputted to the camera according to the count value and the width of the count signal comprises:
- adding 1 to the count value;
- calculating a current clock width according to the count value and the width;
- determining whether the current clock width is smaller than a default clock width;
- making the frame control signal have a high potential if the current clock width is smaller than the default clock width;
- and
- making the frame control signal have a low potential if the current clock width is not smaller than the default clock width.
Dependencies are inferred from the claim text.