Charge pumps, logic circuits including charge pumps, logic devices including logic circuits, and methods of operating logic circuits

A GaN logic circuit, comprising:

• an input node configured to receive an input voltage;
• a first pull up transistor configured to pull up an output voltage in response to the input voltage;
• a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied, the first depletion mode transistor configured to control the first pull up transistor by adjusting a first saturation current through the first depletion mode transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage;
• a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor;
• and
• a first current source configured to discharge a second saturation current to ground when the input voltage has a first level, and to provide the second saturation current to the first depletion mode transistor to adjust the gate voltage difference when the input voltage has a second level.

A logic device, comprising:

• a logic gate configured to receive a pair of input signals and performs a logic operation on the received input signals to generate an intermediate signal;
• and
• a GaN inverter configured to receive the intermediate signal and generate an output signal, the inverter comprising:
• an input node configured to receive the intermediate signal;
• a first pull up transistor configured to pull up the output signal in response to the intermediate signal;
• a depletion mode transistor having a first gate to which a first gate voltage applies and a second gate to which a second gate voltage applies, the depletion mode transistor configured to control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage;
• a capacitor having a first end coupled to the depletion mode transistor and a second end coupled to the first pull up transistor;
• and
• a second pull up transistor configured to pull up a voltage at the first end of the capacitor to a power supply voltage when the intermediate signal has a first level, and make the first end of the capacitor float when the intermediate signal has a second level.