Method and system for fabricating unique chips using a charged particle multi-beamlet lithography system
AssigneeASML Netherlands B.V.
InventorsMarcel Nicolaas Jacobus van Kervinck, Vincent Sylvester Kuiper
Life of this patent
Estimating the term…
Abstract
A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system (301A-301D). The maskless lithographic exposure system comprises a lithography subsystem (316) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine (1) or ebeam machine. The method comprises introducing unique chip design data (430) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.
Claims20
An electronic device, which is a member of a set of semiconductor chips, comprising:
- a common design layout part that is the same for all of the semiconductor chips of the set;
- and
- a non-common design layout part that is the same for only a subset of the semiconductor chips of the set,
- wherein the common design layout part and the non-common design layout part are formed in a plurality of layers, and
- wherein the non-common design layout part includes at least one of:
- connections between a metal layer and a gate in a contact layer of the plurality of layers, or a P- or N-doped active region of a transistor of one of the plurality of layers.
An electronic device, which is a member of a set of semiconductor chips, comprising:
- a common design layout part that is the same for all of the semiconductor chips of the set;
- and
- a non-common design layout part that is the same for only a subset of the semiconductor chips of the set,
- wherein the common design layout part and the non-common design layout part are formed in three or more layers, and
- wherein the non-common design layout part is formed on at least a first one of the layers having a second one of the layers above the first layer and having a third one of the layers below the first layer.
A method for manufacturing an electronic device that is a member of a set of semiconductor chips, the method comprising:
- forming a common design layout part that is the same for all of the semiconductor chips of the set;
- and
- forming a non-common design layout part that is the same for only a subset of the semiconductor chips of the set and is different for other ones of the semiconductor chips of the set, wherein the non-common design layout part includes at least one of:
- connections between a metal layer and a gate in a contact layer of a plurality of layers or a P- or N-doped active region of a transistor of one of a plurality of layers.
Dependencies are inferred from the claim text.