Semiconductor devices and semiconductor systems calibrating termination resistance

A semiconductor system comprising:

• a controller configured to output a command address, a first chip selection signal, a second chip selection signal and a second reference voltage set to a voltage level greater than a first reference voltage;
• and
• a semiconductor device, including a first rank and a second rank, configured to receive the command address, the first chip selection signal, and the second chip selection signal and configured to calibrate a termination resistance value of the first rank based on the command address and the first chip selection signal and to calibrate a termination resistance value of the second rank based on the command address and the second chip selection signal;
• wherein the first rank calibrates the termination resistance value of the first rank to a first resistance value based on the command address and the first chip selection signal when a write operation is performed on the first rank;
• wherein the first rank calibrates the termination resistance value of the first rank to a second resistance value based on the second chip selection signal when a write operation is performed on the second rank;
• wherein the first resistance value is different from the second resistance value;
• and
• wherein a termination resistance value corresponds to a value that impedance matches a receiving end for data during the write operation.

A semiconductor system comprising:

• a controller configured to output a command address, a first chip selection signal, a second chip selection signal, and a third chip selection signal;
• and
• a semiconductor device including a first rank, a second rank, and a third rank configured to receive the command address, the first chip selection signal, the second chip selection signal, and the third chip selection signal and configured to calibrate a termination resistance value of the first rank based on the command address and the first chip selection signal, to calibrate a termination resistance value of the second rank based on the command address and the second chip selection signal, and to calibrate a termination resistance value of the third rank based on the command address and the third chip selection signal;
• wherein the first rank calibrates the termination resistance value of the first rank to a first resistance value based on the command address and the first chip selection signal when a write operation is performed on the first rank;
• wherein the first rank calibrates the termination resistance value of the first rank to a second resistance value based on the second chip selection signal and the third chip selection signal when the write operation is not performed on the first rank
• wherein the first resistance value is different from the second resistance value;
• and
• wherein a termination resistance value corresponds to a value that impedance matches a receiving end for data during the write operation.

A semiconductor device comprising:

• a first rank configured to calibrate a first termination resistance value of the first rank to a first resistance value when a write command is generated from a command address during a state in which a first chip selection signal is received including a first pulse driven to a voltage level equal to or higher than a first reference voltage;
• and
• a second rank configured to calibrate a second termination resistance value of the second rank to the first resistance value when the write command is input during a state in which a second chip selection signal is received including a second pulse driven to the voltage level equal to or higher than the first reference voltage;
• wherein the first rank calibrates the termination resistance value of the first rank to a second resistance value when a write operation is performed on the second rank and the second chip selection signal is received including a pulse driven to a voltage level equal to or higher than a second reference voltage set higher than the first reference voltage;
• wherein the first resistance value is different from the second resistance value;
• and
• wherein a termination resistance value corresponds to a value that impedance matches a receiving end for data during the write operation.