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US 12,322,468 B2Granted
Conditional write back scheme for memory
AssigneeMicron Technology, Inc.
InventorsRichard C. Murphy, Glen E. Hush, Honglin Sun
Life of this patent
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Abstract
Apparatuses and methods can be related to implementing a conditional write back scheme for memory. The data may be stored by memory cells of a memory array. The data may be moved to sense circuitry. The data can be conditionally held by the sense circuitry while a plurality of operations is performed. The results of the plurality of operations can dictate whether to commit the data to the memory cells.
Claims20
A system, comprising:
- a host configured to provide a command to activate transactional memory;
- a memory device coupled to the host and configured to:
- responsive to receipt of the command, activate transactional memory of the memory device;
- activate a row of a memory array of the memory device to move data to a plurality of sense amplifiers by latching the data in the plurality of sense amplifiers that comprises the transactional memory;
- deactivate the row of the memory array responsive to the data being latched by the plurality of sense amplifiers to allow a processing resource to determine whether it is secure to commit the data to the row of memory cells;
- and
- activate the row of the memory array responsive to determining that it is secure to commit the data to the row.
4 more elements
A method comprising:
- writing a register of a memory device to a state to activate transactional memory of the memory device;
- activating a row of a memory array of the memory device to move data stored in the row of memory cells to the transactional memory responsive to the register being written to the state;
- deactivating the row of the memory array responsive to the data being stored by the transactional memory to allow a processing resource to perform a plurality of operations to determine whether it is secure to commit the data to the row of memory cells, wherein deactivating the row resets the memory cells such that the memory cells do not store the data;
- and
- determining whether to activate the row to move the data to the memory cells from the transactional memory comprising a different row of memory cells of the memory array or refrain from activating the row responsive a result of the plurality of operations.
2 more elements
An apparatus comprising:
- a memory array;
- and
- a row decode coupled to the memory array and configured to:
- transfer data from a first row of memory cells to a redundant row of memory cells such that the first row of memory cells does not store the data;
- retain the data in the redundant row of memory cells to allow a processing resource to perform a plurality of operations to determine whether it is secure to commit the data to the first row of memory cells;
- responsive to determining that it is not secure to commit the data to the first row of memory cells, receive a signal to commit the data to a second row of memory cells of the memory array;
- and
- transfer the data from the redundant row of memory cells to the second row of memory cells responsive to receipt of the signal to move the data from the redundant row of memory cells to the second row of memory.
5 more elements
Dependencies are inferred from the claim text.