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US 12,322,456 B2Granted
Digital verify failbit count (VFC) circuit
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsTeng Chen, Masao Kuriyama
Life of this patent
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Abstract
A verify failbit count (VFC) circuit includes a counter circuit and a transcoder circuit. The counter circuit includes a counter. The counter is configured to count one or more fail bits based on results of a verification operation of a memory device to obtain a count result in unary format. The transcoder circuit includes a transcoder coupled to the counter. The transcoder is configured to transcode the count result in unary format to a transcoded result in binary format.
Claims20
A verify failbit count (VFC) circuit comprising:
- a counter circuit including a counter, the counter being configured to count one or more fail bits based on results of a verification operation of a memory device to obtain a count result in unary format, the counter including:
- a power-supply transistor, a first terminal of the power-supply transistor being configured to be coupled to a power supply;
- and
- a plurality of counter stages each including:
- a counter latch;
- and
- a transistor string coupled between the counter latch and a second terminal of the power-supply transistor, the transistor string including a plurality of transistors coupled in series;
- and
- a transcoder circuit including a transcoder coupled to the counter, the transcoder being configured to transcode the count result in unary format to a transcoded result in binary format.
6 more elements
A memory device comprising:
- a memory cell array including one or more memory sections each including one or more memory cells;
- a buffer circuit including one or more buffers each coupled to one of the one or more memory sections;
- and
- a verify failbit count (VFC) circuit coupled to the buffer circuit and including:
- a counter circuit including a counter, the counter being configured to count one or more fail bits based on results of a verification operation of one of the one or more memory sections to obtain a count result in unary format, the counter including:
- a power-supply transistor, a first terminal of the power-supply transistor being configured to be coupled to a power supply;
- and
- a plurality of counter stages each including:
- a counter latch;
- and
- a transistor string coupled between the counter latch and a second terminal of the power-supply transistor, the transistor string including a plurality of transistors coupled in series;
- and
- a transcoder circuit including a transcoder coupled to the counter, the transcoder being configured to transcode the count result in unary format to a transcoded result in binary format.
10 more elements
A memory system comprising:
- a memory device including:
- a memory cell array including one or more memory sections each including one or more memory cells;
- a buffer circuit including one or more buffers each coupled to one of the one or more memory sections;
- and
- a verify failbit count (VFC) circuit coupled to the buffer circuit and including:
- a counter circuit including a counter, the counter being configured to count one or more fail bits based on results of a verification operation of one of the one or more memory sections to obtain a count result in unary format, the counter including:
- a power-supply transistor, a first terminal of the power-supply transistor being configured to be coupled to a power supply;
- and
- a plurality of counter stages each including:
- a counter latch;
- and
- a transistor string coupled between the counter latch and a second terminal of the power-supply transistor, the transistor string including a plurality of transistors coupled in series;
- and
- a transcoder circuit including a transcoder coupled to the counter, the transcoder being configured to transcode the count result in unary format to a transcoded result in binary format;
- and
- a memory controller coupled to the memory device and configured to control operation of the memory device.
13 more elements
Dependencies are inferred from the claim text.