DSB operation with excluded region

A method, comprising:

• receiving, by a first processor of a computer system, a first data barrier operation request from a second processor of the computer system;
• based on receiving the first data barrier operation request from the second processor, the first processor ensuring that outstanding load/store operations executed by the first processor that are directed to addresses outside of a memory exclusion region have been completed;
• and
• responding, by the first processor and to the second processor, that the first data barrier operation request is complete at the first processor, even in the case that one or more load/store operations directed to addresses within the memory exclusion region are outstanding and not complete when the first processor responds that the first data barrier operation request is complete.

A non-transitory computer readable medium having stored thereon design information that specifies a circuit design in a format recognized by a fabrication system that is configured to use the design information to fabricate a hardware integrated circuit that comprises:

• a plurality of processors that are communicatively coupled;
• wherein a first processor of the plurality of processors is configured to:
• issue a first data barrier operation request responsive to a detection of an occurrence of a particular event;
• wherein a second processor of the plurality of processors is configured to:
• receive the first data barrier operation request;
• ensure that outstanding load/store operations executed by the second processor that are directed to addresses outside of an exclusion region have been completed;
• and
• respond to the first processor that the first data barrier operation request is complete at the second processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the second processor responds that the first data barrier operation request is complete.

A system, comprising:

• a first processor and a second processor that are communicatively coupled;
• wherein the first processor is configured to:
• issue a first data barrier operation request responsive to a detection of an occurrence of a particular event;
• wherein the second processor is configured to:
• receive the first data barrier operation request;
• receive a second data barrier operation request after reception of the first data barrier operation request;
• and
• concurrently process the first and second data barrier operation requests based on a detection that the second data barrier operation request is of a different type than the first data barrier operation request.