Double fetch for long burst length memory data transfer
AssigneeIntel Corporation
InventorsKuljit S. Bains, Bill Nale
Life of this patent
Estimating the term…
Abstract
For a memory device where a data fetch accesses N/2 data bits, and the memory device is to transfer N bits over a data burst of length M in response to a read command, the memory device accesses the same bank twice to access the N bits. Instead of accessing N/2 bits from two different banks, the memory device accesses a single bank twice. The memory device can control the timing of the data transfer to enable sending all N data bits to the memory controller for the read command. The memory device can send data as a first transfer of burst length M/2 of a first N/2 data bit portion and a second transfer of burst length M/2 of a second N/2 data bit portion.
Claims24
A memory device, comprising:
- a hardware interface to couple to a memory controller, wherein in response to a read command from the memory controller, the hardware interface is to transfer N data bits over a burst length M;
- a memory array having multiple banks, including a selected bank selected for read access for the read command, wherein the read access to the selected bank is to access N/2 data bits from the selected bank;
- and
- control hardware, wherein in response to the read command, the control hardware is to trigger two consecutive read accesses to the selected bank to access N data bits from the selected bank, a first read access to fetch a first N/2 data bit portion and a second read access to fetch a second N/2 data bit portion, and cause the hardware interface to send data as a first transfer of burst length M/2 of the first N/2 data bit portion and a second transfer of burst length M/2 of the second N/2 data bit portion.
A memory controller, comprising:
- a data interface to couple to a memory device, to receive N data bits over a burst length M in response to a read command;
- a command interface to couple to the memory device, to send the read command to the memory device to read a selected bank of multiple banks of the memory device, wherein read access to the selected bank by the memory device is to access N/2 data bits from the selected bank, wherein the memory device is to perform two consecutive read accesses to the selected bank to access N data bits from the selected bank, a first read access to fetch a first N/2 data bit portion and a second read access to fetch a second N/2 data bit portion;
- and
- a scheduler to schedule the read command with other commands based on the memory device to send data to the data interface as a first transfer of burst length M/2 of the first N/2 data bit portion and a second transfer of burst length M/2 of the second N/2 data bit portion.
A system, comprising:
- a memory device coupled to a memory controller, the memory device and the memory controller to exchange N data bits over a burst length M, the memory device including
- a memory array having multiple banks, including a selected bank selected for read access for a read command from the memory controller, wherein the read access to the selected bank is to access N/2 data bits from the selected bank;
- and
- control hardware, wherein in response to the read command, the control hardware is to trigger two consecutive read accesses to the selected bank to access N data bits from the selected bank, a first read access to fetch a first N/2 data bit portion and a second read access to fetch a second N/2 data bit portion;
- wherein the memory device is to send data as a first transfer of burst length M/2 of the first N/2 data bit portion and a second transfer of burst length M/2 of the second N/2 data bit portion;
- and
- the memory controller including
- a scheduler to schedule the read command with other commands based on the memory device to send data as the first transfer and the second transfer.
Dependencies are inferred from the claim text.