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US 12,321,608 B2Granted
Read cache memory
AssigneeMicron Technology, Inc.
InventorsEugene Feng, Mathew Arcoleo
Life of this patent
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Abstract
The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.
Claims13
An apparatus, comprising:
- a substrate;
- a dynamic random-access memory (DRAM) array formed on a first die coupled to the substrate;
- a NAND array formed on a second die coupled to the first die in a first offset manner;
- a controller formed on a third die coupled to the second die via direct die-to-die bonding;
- and
- a fan-out wafer level packaging (WLP) pad adjacent to the controller, wherein the controller is coupled to the DRAM array via the WLP pad and a first bonding wire and coupled to the NAND array via the WLP pad and a second bonding wire, and wherein data is moved from the DRAM array to the NAND array via the WLP pad, the first bonding wire, and the second bonding wire.
3 more elements
A method, comprising:
- coupling a first die to a substrate and forming a first dynamic random-access memory (DRAM) array on the first die;
- offsetting a second die from the first die and forming a second DRAM array on the second die;
- offsetting a third die from the second die and forming a first NAND array on the third die;
- offsetting a fourth die from the third die and forming a second NAND array on the fourth die;
- forming a fifth die on the fourth die, wherein the fifth die includes a fan-out wafer level packaging (WLP) pad adjacent to a controller;
- coupling the controller to the first DRAM array via the WLP pad and a first bonding wire;
- coupling the controller to the first NAND array via the WLP pad and a second bonding wire;
- and
- moving data from the first DRAM array to the first NAND array via the WLP pad, the first bonding wire, and the second bonding wire.
6 more elements
An apparatus, comprising:
- a substrate;
- a first dynamic random-access memory (DRAM) array formed on a first die coupled to the substrate in a first offset;
- a second DRAM array formed on a second die coupled to the first die in a second offset manner, wherein the second offset exposes a single row of pads of the second DRAM array;
- a first NAND array formed on a third die coupled to the second die in a third offset manner;
- a second NAND array formed on a fourth die coupled to the third die in a fourth offset manner;
- a controller formed on a fifth die coupled to the fourth die;
- and
- a fan-out wafer level packaging (WLP) pad adjacent to the controller, wherein the controller is coupled to the first DRAM array via the WLP pad and a first bonding wire and coupled to the first NAND array via the WLP pad and a second bonding wire, and wherein data is moved from the first DRAM array to the second NAND array via the WLP pad, the first bonding wire, and the second bonding wire.
5 more elements
Dependencies are inferred from the claim text.