Clock mode determination in a memory system

A method for operating a configurable flash memory device comprising a first clock input port, a second clock input port, a clock output port, a chip enable port, one or more configurable output buffers and a configurable data interface, the method comprising:

• providing a chip enable signal to the chip enable port for enabling the configurable flash memory device;
• providing a first clock input signal to the first clock input port and a second clock input signal to the second clock input port, the second clock input signal being complementary to the first clock input signal;
• configuring the configurable flash memory device into one of a single ended signaling configuration and a differential signaling configuration, the differential signaling configuration for utilizing the first clock input signal and the second clock input signal as differential signals, and the single ended signaling configuration for utilizing one of the first clock input signal and the second clock input signal as a single ended signal;
• configuring the configurable data interface to one of a 1-bit data width and an n-bit data width where n is a non-zero integer greater than 1, and to one of a single data rate configuration and a double data rate configuration, the configurable data interface configured to transfer common data signals carrying at least one of command data, address data, input data and output data;
• configuring the one or more configurable output buffers to one of a plurality of output buffer drive strengths;
• and
• receiving the clock output signal from the clock output port and the output data from the one or more configurable output buffers in synchronization with the clock output signal when the configurable flash memory device is in the double data rate configuration.

A memory system comprising:

• a configurable flash memory device comprising a first clock input port, a second clock input port, a clock output port, a chip enable port, one or more configurable output buffers, and a configurable data interface;
• and
• a memory controller communicatively coupled to the configurable flash memory device, the memory controller configured to:
• provide a chip enable signal to the chip enable port for enabling the configurable flash memory device;
• provide a first clock input signal to the first clock input port and a second clock input signal to the second clock input port, the second clock input signal being complementary to the first clock input signal;
• configure the configurable flash memory device into one of a single ended signaling configuration and a differential signaling configuration, the differential signaling configuration for utilizing the first clock input signal and the second clock input signal as differential signals, and the single ended signaling configuration for utilizing one of the first clock input signal and the second clock input signal as a single ended signal;
• configure the configurable data interface to one of a 1-bit data width an n-bit data width where n is a non-zero integer greater than 1, and to one of a single data rate configuration and a double data rate configuration, the configurable data interface configured to transfer common data signals carrying at least one of command data, address data, input data and output data;
• configure the one or more configurable output buffers to one of a plurality of output buffer drive strengths;
• and
• receive the clock output signal from the clock output port and the output data from the one or more configurable output buffers in synchronization with the clock output signal when the configurable flash memory device is in the double data rate configuration.